Sumitomo Electric Industries, Limited

International Superconductivity Technology Center

Ishikawajima-harima Heavy Industries Co., Ltd.

International Superconductivity Technology Center, the Juridical

Yasuo Namikawa

Shin Harada

Shinsuke Fujiwara

Taro Nishiguchi

Makoto Sasaki

Yuh Shiohara

Takeyoshi Masuda

Shoji Tanaka

Kyoko Okita

Kazuhiro Fujikawa

Keisuke Tanizaki

Hiroki Inoue

Masahiro Egami

Toru Hiyoshi

Keiji Wada

Hiromu Shiomi

Masami Tatsumi

Hideto Tamaso

Yasuji Yamada

Mitsuru Shimazu

Yasuko Torii

Satoshi Koyama

Satomi Itoh

Xin Yao

A GaAs crystal () has &#x394;x(1) not greater than 20 cmin an expression 1 where xrepresents a Raman shift of a first peak attributed to oscillation of a longitudinal optical phonon of GaAs in a Raman spectrum measured at an ith point in measurement of Raman spectra at s points in a (100) plane, xrepresents a Raman shift of an emission line peak of neon, and i and s are each a natural number greater than 0.

GaAs crystal

A GaAs crystal has &#x394;x(1) not greater than 20 cmin an expression 1 where xrepresents a Raman shift of a first peak attributed to oscillation of a longitudinal optical phonon of GaAs in a Raman spectrum measured at an ith point in measurement of Raman spectra at s points in a (100) plane, xrepresents a Raman shift of an emission line peak of neon, and i and s are each a natural number greater than 0.

On a pepitaxial layer, an n-type epitaxial layer and a gate region are formed in this order. A gate electrode is electrically connected to the gate region, and a source electrode and a drain electrode are spaced apart from each other with the gate electrode sandwiched therebetween. A control electrode is used for applying to the pepitaxial layer a voltage that causes a reverse biased state of the pepitaxial layer and the n-type epitaxial layer in an OFF operation.

Lateral junction field-effect transistor

The invention offers a method of producing a semiconductor device that can suppress the worsening of the property due to surface roughening of a wafer by sufficiently suppressing the surface roughening of the wafer in the heat treatment step and a semiconductor device in which the worsening of the property caused by the surface roughening is suppressed. The method of producing a MOSFET as a semiconductor device is provided with a step of preparing a wafermade of silicon carbide and an activation annealing step that performs activation annealing by heating the wafer. In the activation annealing step, the waferis heated in an atmosphere containing a vapor of silicon carbide generated from the SiC piece, which is a generating source other than the wafer

Method of producing semiconductor device and semiconductor device

There is provided a method for manufacturing a SiC semiconductor device achieving improved performance. The method for manufacturing the SiC semiconductor device includes the following steps. That is, a SiC semiconductor is prepared which has a first surface having at least a portion into which impurities are implanted. By cleaning the first surface of the SiC semiconductor, a second surface is formed. On the second surface, a Si-containing film is formed. By oxidizing the Si-containing film, an oxide film constituting the SiC semiconductor device is formed.

Method for manufacturing silicon carbide semiconductor device

A JFET is a semiconductor device allowing more reliable implementation of the characteristics essentially achievable by employing SiC as a material and includes a wafer having at least an upper surface made of silicon carbide, and a gate contact electrode formed on the upper surface. The wafer includes a first p-type region serving as an ion implantation region formed so as to include the upper surface. The first p-type region includes a base region disposed so as to include the upper surface, and a protruding region. The base region has a width (w) in the direction along the upper surface greater than a width (w) of the protruding region. The gate contact electrode is disposed in contact with the first p-type region such that the gate contact electrode is entirely located on the first p-type region as seen in plan view.

Semiconductor device and method for manufacturing the same

A silicon carbide substrate has a first layer facing a semiconductor layer and a second layer stacked on the first layer. Dislocation density of the second layer is higher than dislocation density of the first layer. Thus, quantum efficiency and power efficiency of a light-emitting device can both be high.

Light-emitting device

At least one single crystal substrate, each having a backside surface and made of silicon carbide, and a supporting portion having a main surface and made of silicon carbide, are prepared. In this preparing step, at least one of the backside surface and main surface is formed by machining. By this forming step, a surface layer having distortion in the crystal structure is formed on at least one of the backside surface and main surface. The surface layer is removed at least partially. Following this removing step, the backside surface and main surface are connected to each other.

Method for manufacturing silicon carbide substrate

A first silicon carbide substrate having a first back-side surface and a second silicon carbide substrate having a second back-side surface are prepared. The first and second silicon carbide substrates are placed so as to expose each of the first and second back-side surfaces in one direction. A connecting portion is formed to connect the first and second back-side surfaces to each other. The step of forming the connecting portion includes a step of forming a growth layer made of silicon carbide on each of the first and second back-side surfaces, using a sublimation method of supplying a sublimate thereto in the one direction.

Method for manufacturing semiconductor substrate

Semiconductor substrate

A process of heat-treating II-VI compound semiconductors reduces the electrical resistivity without the decrease in crystallinity resulting from the increase in dislocation density. The process comprises the following steps:(a) placing at least one II-VI compound semiconductor in contact with aluminum in a heat-treating chamber having the inside surface formed by at least one material selected from the group consisting of pyrolytic born nitride, hexagonal-system boron nitride, sapphire, alumina, aluminum nitride, and polycrystalline diamond; and (b) heat-treating the II-VI compound semiconductor or semiconductors in a gaseous atmosphere containing the group II element constituting part of the II-VI compound semiconductor or semiconductors. A II-VI compound semiconductor is heat-treated by the foregoing process. An apparatus for heat-treating II-VI compound semiconductors comprises components for performing the foregoing process.

Process of and apparatus for heat-treating II-VI compound semiconductors and semiconductor heat-treated by the process

This invention relates to a method for the heat treatment of a ZnSe crystal substrate to dope it with Al as a donor impurity, a ZnSe crystal substrate prepared by this heat treatment and a light-emitting device using the ZnSe crystal substrate, in particular, the method for the heat treatment of a ZnSe crystal substrate comprising previously forming an Al film on the substrate, first subjecting the substrate to a heat treatment in a Se atmosphere and then subjecting to a heat treatment in a Zn atmosphere.

Method for the heat treatment of a ZnSe crystal substrate, heat treated substrate and light emission device

A large oxide crystal of high quality is manufactured by increasing the speed of crystal growth without affecting crystal growth. A melt of BaO--CuO as a raw material put in a crucible is heated and melt in the presence of a solid phase precipitate of Y.sub.2 BaCuO.sub.5 and kept at a prescribed temperature. Thereafter, a seed crystal is pulled up while being rotated, with the seed crystal being in contact with the surface of the melt, whereby an oxide crystal having the structure of YBa.sub.2 Cu.sub.3 O.sub.7-x this method, an atmosphere for growing the oxide crystal has an oxygen partial pressure higher than that in an ambient atmosphere.

Growing community of inventors

Itami, Japan

Yasuo Namikawa