Renesas Electronics Corporation

Renesas Technology Corp.

Konica Corporation

Yasumasa Tsukamoto

Koji Nii

Makoto Yabuuchi

Shigeki Ohbayashi

Kengo Masuda

Akio Ueda

Masaru Ushio

Hiroki Ueda

Takaaki Sakai

Yoshinao Kitahara

In a region just below an access gate electrode in an SRAM memory cell, a second halo region is formed adjacent to a source-drain region and a first halo region is formed adjacent to a first source-drain region. In a region just below a drive gate electrode, a third halo region is formed adjacent to the third source-drain region and a fourth halo region is formed adjacent to a fourth source-drain region. The second halo region is set to have an impurity concentration higher than the impurity concentration of the first halo region. The third halo region is set to have an impurity concentration higher than the impurity concentration of the fourth halo region. The impurity concentration of the first halo region and the impurity concentration of the fourth halo region are different from each other.

Static random access memory device with halo regions having different impurity concentrations

In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.

Semiconductor memory device for stably reading and writing data

A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage.

Semiconductor memory device with adjustable selected word line potential under low voltage condition

Semiconductor memory device with adjustable selected work line potential under low voltage condition

The invention provides a semiconductor device capable of reducing wasteful power consumption. The semiconductor device of the invention does not require a refresh operation, and includes memory circuits for storing data, arranged in a matrix form, first signal lines for reading data from the memory circuits, second signal lines for transferring a signal that controls connection between the memory circuits and the first signal lines, a sense amplifier circuit for reading and determining data by detecting a potential change or a current change in the first signal lines, and a mitigating means for mitigating the potential change or the current change in the first signal lines during a period in which the sense amplifier circuit is being activated.

Semiconductor device

A substrate potential setting circuits are provided which control substrate potentials in units of columns of a memory cell array at least in data writing. Upon data writing, the potential of the substrate region of memory cell transistors on a selected column is changed to reduce the data holding characteristics (static noise margin) to ensure high-speed data writing to the memory cells. Data writing is performed at high speed without impairing stability of data retention.

Semiconductor memory device with back gate potential control circuit for transistor in memory cell

An image forming apparatus includes an image forming apparatus body, an image reading apparatus mounted on the upper portion of the apparatus body, and a postprocessing apparatus having a folding unit which folds a sheet. The image forming apparatus includes a selection window which is formed on an operation display unit of the image forming apparatus body and allows selection of a fold surface of a sheet. The selection window displays a three-fold process of folding an upper surface on which an image is formed and a three-fold process of folding a lower surface on which no image is formed.

Image forming apparatus which conveys an image-formed sheet to reverse the sheet and conveys the sheet to a folding unit when a three-fold process of folding a lower surface is selected

An SRAM includes first and second access PMOS transistors in an N well region; first and second driver NMOS transistors in a P well region; a word line; and first and second bit lines. Active regions extend in the same direction, polysilicon wirings for forming gates of each of the MOS transistors extend in the same direction, and drains of the first and second access PMOS transistors are connected to drains of the first and second driver NMOS transistors using first metal wirings without interposing the polysilicon wirings forming the gates of the first and second driver NMOS transistors therebetween, respectively.

Static semiconductor memory device

An image forming apparatus includes: an image reading device for reading images on a document; an image recording device for recording images read by the image reading device on a recording material; an inputting device that makes it possible for an operator to select either area from plural imaginary areas established in advance and to adjust a position in the selected area, for setting, on a given position on the recording material, a recording position for additional information to be recorded on the recording material by the image recording device in addition to the images stated above; and a controller that controls the image recording device for recording the additional information on the recording position that is set by the inputting device.

Growing community of inventors

Tokyo, Japan

Yasumasa Tsukamoto