Fuji Electric Co., Ltd.

Fuji Electric Corporate Research and Developement Ltd.

Fuji Electric Corporate Research & Development Co., Ltd.

Octec, Inc.

Kyushu University

Yasukazu Seki

Noritada Sato

Haruo Nakazawa

Koh Yoshikawa

Kenichi Iguchi

Masaya Yabe

Katsuya Okumura

Katsunori Ueno

Naoki Kumagai

Koichi Hashimoto

Akira Nishiura

Hiroshi Ikenoue

Shinji Ogino

Tatsuo Urushidani

Toshikazu Suzuki

Osamu Ishiwata

Akihiro Ikeda

Tanemasa Asano

Osamu Ishiwate

Taro Toyoda

A semiconductor device having a voltage resistant structure in a first aspect of the present invention is provided, comprising a semiconductor substrate, a semiconductor layer on the semiconductor substrate, a front surface electrode above the semiconductor layer, a rear surface electrode below the semiconductor substrate, an extension section provided to a side surface of the semiconductor substrate, and a resistance section electrically connected to the front surface electrode and the rear surface electrode. The extension section may have a lower permittivity than the semiconductor substrate. The resistance section may be provided to at least one of the upper surface and the side surface of the extension section.

Manufacturing method of semiconductor device having a voltage resistant structure

When p-type impurities are implanted into a SiC substrate using a laser, controlling the concentration is difficult. A p-type impurity region is formed by a laser in a region where the control of the concentration in the SiC substrate is not necessary almost at all. A SiC semiconductor device having withstanding high voltage is manufactured at a lower temperature process compared to ion implantation process. A method of manufacturing a silicon carbide semiconductor device includes forming, on one main surface of a first conductivity-type silicon carbide substrate, a first conductivity-type drift layer having a lower concentration than that of the silicon carbide substrate; forming, on a front surface side of the drift layer, a second conductivity-type electric field control region by a laser doping technology; forming a Schottky electrode in contact with the drift layer; and forming, on the other main surface of the silicon carbide substrate, a cathode electrode.

Method of manufacturing silicon carbide semiconductor device including forming an electric field control region by a laser doping technology

Semiconductor device having a voltage resistant structure

Impurity elements are doped at a high concentration exceeding a thermodynamic equilibrium concentration into a solid material having an extremely small diffusion coefficient of the impurity element. A method for doping impurities includes steps for depositing source film made of material containing impurity elements with a film thickness on a surface of a solid target object (semiconductor substrate) made from the solid material. The film thickness is determined in consideration of irradiation time per light pulse and the energy density of the light pulse. The method also includes a step for irradiating the source film by the light pulse with the irradiation time and the energy density so as to dope the impurity elements into the target object at a concentration exceeding a thermodynamic equilibrium concentration.

Method for doping impurities, method for manufacturing semiconductor device

A Schottky electrode is formed on an n-type SiC base member with an Al--Ti alloy or by laying Al films and Ti films alternately, and a resulting structure is subjected to a heat treatment of 600.degree. C. to 1,200.degree. C. A p-type SiC layer may be formed around the Schottky junction so as to form a p-n junction with the n-type SiC base member.

Manufacturing method of SiC Schottky diode

A conductivity-modulated-type MOSFET. A base layer is on a drain layer, and a first semiconductor region, having the opposite conductivity-type as the base layer, is in the base layer. An insulation layer is on the portion of the first semiconductor region, and a gate is on the insulation layer. A second semiconductor region, having the same conductivity type as the base layer is in the second semiconductor layer at a periphery of the MOSFET.

Conductivity-modulated-type MOSFET

A channel in which electron current is supplied from n.sup.+ type source layer to an n.sup.- type base layer is formed in a thyristor portion by using a first gate electrode to have an electrical connection in a thyristor state. Injection of hole current to a p type base layer, which is necessary to maintain the thyristor state is extracted to a source terminal by a control MOSFET portion including a second gate electrode a turn-off time and the state of this device is changed to the transistor state similar to that in the IGBT so that a short switching time turn-off is realized.

Semiconductor device having thyristor structure

Horizontal deflection circuits are disclosed which permit high-frequency operation through use of conductivity modulation MOS FET devices. Distortion of the horizontal deflection coil voltage is avoided by inclusion of compensation means utilizing an inductance to produce delay in the increase in magnitude of current flow during reverse recovery current flow. Use of a compensation means including an inductor and diode in parallel combination provides additional benefits of oscillation suppression.

Horizontal deflection circuit for high-frequency scanning

The present invention relates to a method of producing an insulated gate bipolar transistor, of a vertical insulated gate field effect transistor. In the present invention a window portion is formed on a low-temperature oxide film and a polysilicon layer deposited on a polysilicon layer, which serves as a gate, and the ions of impurities are implanted while using these as a mask, thereby forming a P-base layer. The ions of impurities are then again implanted using this mask to form a P.sup.++ layer instead of using a conventional resist mask. Accordingly, in the present invention, the P.sup.++ layer is formed in self alignment with the edge of the polysilicon gate. Since there is no positional deviation due to inaccurate mask positioning which may be produced when a mask such as a resist is used, positional accuracy is enhanced which hereby eliminates latchup.

Method of producing insulated gate bipolar tranistor

A conductivity modulation MOSFET with two base layers formed over a drain layer. A trench with a lower portion and an upper portion is formed in the second base layer. The lower portion of the trench has a fixed width, and the upper portion of the trench has a steadily increasing width relative to the lower portion. A gate is placed in the lower portion of the trench, while the source regions are formed in the second base region alongside the side walls of the upper trench portion.

Conductivity modulation buried gate trench type MOSFET

A conductivity modulation MOSFET having a second buffer layer is disclosed. The second buffer layer is thinner and has a higher impurity concentration than the first buffer layer. The second buffer layer is interspersed with heavy metal atoms such as gold and platinum that facilitate recombination of holes and electrons thereby shortening turn off time. However, because of the relative thinness of the second layer compared to the first layer, the second layer has almost no influence in increasing ON resistance.

Conductivity modulation type MOSFET

The present invention relates to a method of producing a vertical insulated gate field effect transistor. In the present invention a window portion is formed on a polysilicon layer which serves as a gate, by selectively etching the layer so as to leave the central portion intact. Ions of impurities are implanted while using the polysilicon layer having the window portion as a mask. Thereby a phase layer is formed and the ions of impurities are again implanted from the window portion, forming the N.sup.+ source region. Since this method is different from a conventional method in that positioning using a special resist mask is unnecessary, the N.sup.+ source region is formed by self alignment with a high efficiency and a high accuracy without any positional deviation caused by inaccurate positioning of a mask.

Method of producing insulated gate MOSFET employing polysilicon mask

A conductivity modulated MOSFET is composed of a MOSFET formed according to SOI technique utilizing two polycrystalline silicon layers deposited on a semiconductor substrate through an oxide film, and a vertical bipolar transistor formed within the semiconductor substrate. Therefore, electrons and positive holes pass through different passages respectively, and any parasitic thyristor is not formed as in the conventional conductivity modulated MOSFET with a MOSFET built in the semiconductor substrate, and thus there is no possibility of causing the latch up phenomenon.

Conductivity modulated MOSFET

A semiconductor-based radiation detector comprising a semiconductor substrate and an amorphous semiconductor layer formed on one surface of the substrate, one electrode being applied to the substrate and one to the amorphous layer, the electrodes formed on the amorphous semiconductor layer consisting of closely spaced, interconnected conductive strips which are substantially uniformly arranged over the entire radiation-incident surface of the amorphous semiconductor layer whereby the electrostatic capacitance appearing between the electrodes of the detector is significantly reduced without significantly changing the area of the detector that responds to radiation.

Novel semiconductor-based radiation detector

A semiconductor device for detecting gamma radiation displaying superior linearity of response to radiation without showing any energy dependency even if the gamma rays have the high energy is formed using an annular depletion region surrounded by non-depletion regions. The size of the regions is selected so that the distance from the edge of the depletion to the most distant point of the non-depletion region is at least about equal to the mean range of the highest energy gamma ray to be measured.

Growing community of inventors

Kanagawa, Japan

Yasukazu Seki