Kabushiki Kaisha Toshiba

Toshiba Kikai Kabushiki Kaisha

Yasukazu Mase

Masahiro Abe

Tomie Yamamoto

Masaharu Aoyama

Toshihiko Katsura

Osamu Hirata

Takashi Ajima

Yoshitaka Matsui

Shoichi Shin

Masahiro Ishida

Masafumi Tsunada

Takeshi Kubota

Takeshi Sunada

Toshihiko Kitamura

Toshio Oishi

As shown in FIG. , a wiring pattern of a semiconductor integrated circuit device of the present invention comprises a wiring portion extending from a connection hole and a connection portion located on the connection hole and having a matching allowance with respect to said connection hole on said wiring portion side being formed wider than a predetermined matching allowance by a predetermined width with which a required yield of successful matching can be assured.

Wiring pattern of semiconductor integrated circuit device

A CMP apparatus is used to subject a target surface of a semiconductor wafer to a polishing treatment, by moving the target surface and a polishing surface of a polishing cloth relative to each other while supplying a polishing liquid between the target surface and the polishing surface. Electric resistance is measured between pairs of measuring points arranged on opposite sides of dicing lines on the target surface, while subjecting the target surface to the polishing treatment. The polishing treatment is caused to be ended by comparing detected values of a changing rate in measured values of the electric property with a reference value set to correspond to an end point of the polishing treatment.

Chemical mechanical polishing apparatus and method

Provided is a polishing apparatus which comprises a polishing mechanism for polishing a wafer taken out from a cassette, an attaching-detaching device for attaching to and detaching the wafer from the polishing mechanism, a device for cleaning the polished wafer, and a transportation device for transporting the wafer between the cassette, polishing mechanism, attaching-detaching device, and cleaning device. These devices are arranged individually in compartments. A working chamber is divided into a plurality of compartments by means of partitioning devices. A device for polishing a workpiece is set in one of the compartments. The apparatus is also provided with communication devices for internally connecting the adjacent compartments which are divided by the partitioning devices. The apparatus may further comprise devices for individually controlling the respective internal pressures of the compartments or a device for generating an air flow in the form of a laminar flow in each of the compartments.

Polishing apparatus

As shown in FIG. 4, a wiring pattern of a semiconductor integrated circuit device of the present invention comprises a wiring portion extending from a connection hole and a connection portion located on the connection hole and having a matching allowance with respect to said connection hole on said wiring portion side being formed wider than a predetermined matching allowance by a predetermined width with which a required yield of successful matching can be assured.

Method for patterning wirings of semiconductor integrated circuit device

A conductive film is formed on first and second prospective lower wiring layer formation regions on a semiconductor substrate and a prospective isolation region between the lower wiring layers. An insulating interlayer is formed on the semiconductor substrate including this conductive film and is partially removed to obtain an opening in which the conductive film is exposed. In addition, an upper wiring layer is formed on the upper surface of the semiconductor substrate. The conductive film and an upper wiring portion located on the conductive film are simultaneously and selectively removed to obtain isolated upper layer portions and isolated conductive film portions. Alternatively, two wiring portions each having at least two lower wiring portions electrically insulated from each other and adjacent to each other are formed on a semiconductor substrate having a stepped portion, and an insulating interlayer is formed thereon. The insulating interlayer is removed until the first and second wiring portions are exposed. In addition, the stepped portion formed in the second wiring portion is buried with a third insulating film. A method of forming a highly reliable multilayered wiring structure at a high yield can be obtained.

Method of forming multilayered wiring structure of semiconductor device

Measurement of temperature - internal stress characteristics of an Al thin film formed on an Si substrate is performed. The amount of an impurity or impurities mixed in the thin f ilm can be obtained in accordance with the measured characteristics. A migration start temperature of Al atoms in the thin film in the characteristics obtained when the temperature is increased is fed back as information to the thin film formation step, thereby controlling an impurity amount in an atmosphere for forming the thin film.

Method of controlling metal thin film formation conditions

In a method for determining an end of cleaning of a semiconductor manufacturing apparatus according to the invention, when the interior of a semiconductor substrate process chamber of the semiconductor manufacturing apparatus is cleaned by dry etching using plasma discharge, a constant current or voltage is supplied from a high-frequency power source to discharge electrodes during plasma discharge, an impedance between the electrodes or a temperature in the process chamber is monitored, a time point at which the impedance or temperature is abruptly changed is detected, and this time point of detection is determined to be an end of cleaning.

Method of determining end of cleaning of semiconductor manufacturing

An insulation film is formed on a semiconductor substrate in which semiconductor elements are formed. A plurality of wiring layers and interlaid insulation films are alternately laminated on the insulation film. The design margins of the laminated wiring layers and via holes formed in the interlaid insulation films are set to be larger as they are set at a higher level. The design margin is determined by using the focus margin, mask misalignment due to the mask alignment accuracy, pattern size conversion error, warp of the semiconductor substrate and irregularity of the surface of the semiconductor substrate as parameters.

Multi-layered wiring structure of semiconductor integrated circuit device

An apparatus for cleaning semiconductor devices has a mixing section for mixing a chemical solution with pure water. A semiconductor substrate to be cleaned is placed on a support. An ultrasonic generator applies ultrasonic vibrations to the supplied pure water. The mixing section mixes a predetermined chemical solution with the pure water applied with the ultrasonic vibrations and supplies a desired pure water solution onto the semiconductor substrate.

Method and apparatus for cleaning semiconductor devices

A semiconductor device has a first interconnection pattern formed on a semiconductor substrate, and a second interconnection pattern located in and over a through hole formed at a composite insulating layer structure. The composite insulating layer structure is constituted by a first inorganic insulating film and an organic insulating film. At a peripheral region of the second interconnection pattern, the organic insulating film is partially eliminated to form an eliminated portion. The semiconductor device also has a second inorganic insulating film which is formed over the organic insulating film and is directly formed on the first inorganic insulating film, via the eliminated portion.

Semiconductor device having a composite insulating interlayer

A plasma chemical vapor deposition apparatus comprises a reaction chamber, electrodes provided in the reaction chamber and a side wall constituting part of the reaction chamber and having a wafer access opening, at least the side wall having its surface portion covered with an insulating member. The insulating member prevents abnormal discharge between the electrodes and side wall.

Plasma chemical vapor deposition apparatus

A method for manufacturing semiconductor devices comprising the steps of forming a first wiring pattern including first and second lower layers on a semiconductor body, forming an insulation film which covers the first wiring pattern, forming a first hole of 1.5 .mu.m and a second hole of 3 .mu.m in first and second areas of the insulation film which lie over the first and second lower layers, forming a second wiring pattern having first and second upper layers respectively connected to the first and second lower layers via the first and second holes. In the method, the hole formation step includes the substeps of forming a resist film which covers the insulation film, forming a resist pattern by effecting the photolithographic process of exposing the insulation film to light by using a mask pattern having a first hole defining area of 1.5 .mu.m and a second hole defining area of 2.4 .mu.m, and etching the insulation film with the resist pattern used as a mask. The exposing light amount used in the resist pattern formation substep is previously determined so that the size of the first hole can be set equal to that of the first hole defining area, and the reduced amount of the second hole defining area is previously determined so that the size of the second hole obtained under the determined exposing light amount can be set to 3 .mu.m.

Growing community of inventors

Fujisawa, Japan

Yasukazu Mase