Fujitsu Corporation

Yasuhito Takahashi

Solomon I Beilin

Wen-chou Vincent Wang

Michael G Peters

Mark Thomas McCormack

Michael G Lee

Hunt Hang Jiang

William T Chou

James J Roman

Kenji Iida

Norikazu Ozaki

Albert Wong Chan

Yuichiro Ohta

Toshiro Katsube

Hiroyuki Katayama

Masaru Sumi

Yasunaga Kurokawa

Kazuo Nakano

Nobuyuki Hayashi

Tomoyuki Abe

Tetsuzo Yoshimura

Motoaki Tani

Masaaki Inao

Hitoshi Suzuki

Lei Zhang

Hideaki Yoshimura

Thomas Joel Massingill

Dashun Steve Zhou

Kei Fukui

Kazuya Arai

Takashi Shuto

Shinpei Ikegami

David Dung Ngo

Yoshiyasu Saeki

Hnin Nway San Nang

A semiconductor chip mounting layer of a package substrate unit includes an insulation layer, a conductive seed metal layer formed on the top surface of the insulation layer, conductive pads formed on the top surface of the conductive seed metal layer, metal posts formed substantially in the central portion on the top surface of the conductive pads, and a solder resist layer that is formed to surround the conductive pads and the metal posts.

Package substrate unit and method for manufacturing package substrate unit

A method for producing a circuit board having an integrated electronic component comprising providing a circuit board substrate having a first substrate surface and a second substrate surface, securing an integrated electronic component to the first substrate surface, and disposing a first dielectric layer on the first substrate surface and over the first integrated electronic component. The method additionally includes disposing a metallic layer on the first dielectric layer to produce an integrated electronic component assembly, producing in the integrated electronic component assembly at least one via having a metal lining in contact with the metallic layer, and disposing a second dielectric layer over the via and over the metallic layer. At least one metal-lined opening is formed in the second dielectric layer and in the first dielectric layer to expose at least part of the integrated electronic component, and to couple the metal lining of the opening to the first integrated electronic component to produce a circuit board having at least one integrated electronic component. A multi-layer printed circuit board having at least one prefabricated, integrated electronic component.

Method of embedding components in multi-layer circuit boards

A multilayer wiring board is composed of a core portion, a first wiring portion and a second wiring portion. The core portion includes a core insulating layer containing a carbon fiber material. The first wiring portion is bonded to the core portion and has a laminated structure including at least a first insulating layer and a first wiring pattern, the first insulating layer containing glass cloth. The second wiring portion is bonded to the first wiring portion and has a laminated structure including at least a second insulating layer and a second wiring pattern. The core portion, the first wiring portion and the second wiring portion are arranged in a stack.

Multilayer wiring board

A wiring board includes a core layer and a pair of multilayer wiring portions. The core layer, having an upper surface and a lower surface, is formed from a resin composite which contains resin filler and encloses several pieces of carbon fiber cloth. One of the multilayer wiring portions is stacked on the upper surface of the core layer, while the other is stacked on the lower surface of the core layer. Each multilayer wiring portion is composed of a number of insulating layers and wiring patterns stacked alternately with the insulating layers. The wiring patterns of the upper and the lower wiring portions are connected to each other by conductors extending through the entire thickness of the core layer.

Wiring board with core layer containing inorganic filler

An optoreflective structure for reflecting an optical signal following a path defined by an optical waveguide comprising a first cladding layer having a first planar cladding surface; a waveguide disposed on the first cladding layer; and a second cladding layer disposed on the waveguide and having a second planar cladding surface. The first cladding layer, the second cladding layer and the waveguide terminate in a generally dove-tailed structure having a beveled planar surface. An optoreflector is disposed on the beveled planar surface for a changing direction of an optical signal passing through the waveguide. Methods of producing the optoreflective structure are disclosed.

Single and multilayer waveguides and fabrication process

An optical apparatus including an optical substrate having an embedded waveguide and an optical device adapted to receive light transmitted from an end of the waveguide. The optical apparatus includes a coupling structure for coupling the optical device to the substrate. The coupling structure has a thin metallic layer with an aperture. At least a portion of the optical device is disposed in the aperture. A method for making an optical apparatus comprising forming an optical substrate having a waveguide embedded therein; depositing a metal layer over an end of the waveguide; and depositing a polymeric layer over the metal layer. An aperture is formed in the metal layer and in the polymeric layer by removing a portion of the metal layer and a portion of the polymeric layer disposed over the end of the waveguide. The method for making an optical apparatus also comprises inserting at least a portion of an optical device within the aperture so that the optical device is positioned to receive light from the first end of the waveguide.

Optical coupling structures and the fabrication processes

A conductive composition, and articles and methods using the conductive composition are disclosed.

Conductive composition

Device modules with pins and methods for making device modules with pins are disclosed. One embodiment is directed to a method including forming a polymeric circuit structure having a first side and a second side on a substrate. The formed first side is adjacent to the substrate. A pin is bonded to the second side of the polymeric circuit structure. At least a portion of the substrate is removed to expose at least a portion of the first side of the polymeric circuit structure, and a device is mounted on the first side of the polymeric circuit structure.

Modules with pins and methods for making modules with pins

Methods for forming multilayer circuit structures are disclosed. In some embodiments, conductive layers, dielectric layers and conductive posts can be formed on both sides of a circuitized core structure. The conductive posts are disposed in the dielectric layers and can be stacked to form a generally vertical conduction pathway which passes at least partially through a multilayer circuit structure. The formed multilayer circuit structures can occupy less space than corresponding multilayer circuit structures with stacked via structures.

Multilayer circuit structure build up method

A process for fabricating thin multi-layer circuit boards. A substrate is disposed over a heat-accumulating block adjacent thereto so that it is uniformly heated from the back side thereof during the pre-baking.

Process for fabricating a thin multi-layer circuit board

Methods for making circuit substrates and electrical assemblies are disclosed. A conductive composition is disposed between confronting conductive regions and can be cured to form a via structure. The conductive composition includes conductive particles and a carrier. The carrier can include a fluxing agent and an epoxy-functional resin having a viscosity of less than about 1000 centipoise at 25&deg; C.

Methods for making circuit substrates and electrical assemblies

An interposer for providing power, ground, and signal connections between an integrated circuit chip or chips and a substrate. The inventive interposer includes a signal core and external power/ground connection wrap. The two sections may be fabricated and tested separately, then joined together using z-connection technology. The signal core is formed from a conductive power/ground plane positioned between two dielectric layers. A patterned metal layer is formed on each dielectric layer. The two metal layers are interconnected by a through via or post process. The conductive power/ground plane functions to reduce signal cross-talk between signal lines formed on the two patterned metal layers. The power/ground wrap includes an upper substrate positioned above the signal core and a lower substrate positioned below the signal core. The upper and lower substrates of the power/ground wrap are formed from a dielectric film having a patterned metal layer on both sides, with the patterned layers connected by a through via or post process. The two power/ground wrap substrates may be formed separately or from one substrate which is bent into a desired form (e.g., a &ldquo;U&rdquo; shape). The two power/ground substrates are maintained in their proper alignment relative to the signal core and to each other by edge connectors which are also connected to the signal core's intermediary power/ground plane.

Reduced cross-talk noise high density signal interposer with power and ground wrap

Several inventive features for increasing the yield of substrate capacitors are disclosed. The inventive features relating to selective placement of insulating layers and patches around selected areas of the capacitor's main dielectric layer. These insulating layers and defects prevent certain manufacturing processing steps from creating pin-hole defects in the main dielectric layer. The inventive features are suitable for any type of material for the main dielectric layer, and are particularly suited to anodized dielectric layers.

Power conducting substrates with high-yield integrated substrate capacitor

A thin multi-layer circuit board having alternately stacked wiring pattern layers, including a top wiring pattern layer and insulating layers on an insulating plate-like substrate. The wiring pattern layers are electronically connected through vias in the insulating layers to form a predetermined circuit pattern by said wiring pattern layers. A metallic barrier layer is formed on the top wiring pattern layer, except at an exclusion zone of the metallic barrier layer. An electronic part-mounting pad layer and a remodeling pad layer are formed on the metallic barrier layer. The remodeling pad layer is arranged adjacent the electronic part-mounting pad layer, with the exclusion zone therebetween.

Thin multi-layer circuit board having a remodeling pad layer and a metallic barrier layer with an exclusion zone

An encapsulation process for flip-chip bonding chips to a substrate encapsulates solder balls on the chip in a separate encapsulation process in which the chip is coated with encapsulation layer and then a portion of the encapsulation layer is removed to expose a portion of the solder balls.

Growing community of inventors

Nagano, Japan

Yasuhito Takahashi