Renesas Electronics Corporation

Renesas Technology Corp.

Other

Hitachi, Ltd.

Hitachi Engineering Co., Ltd.

Hitachi Ulsi Engineering Corp.

Yasuhisa Shimazaki

Noriaki Maeda

Masanao Yamaoka

Masao Morimoto

Ken Shibata

Kiyotada Funane

Shigenobu Komatsu

Koichiro Ishibashi

Masanori Isoda

Yoshihiro Shinozaki

Kenichi Osada

Koji Nii

Toshiaki Sano

Yasuyuki Okuma

Susumu Narita

Shinichi Yoshioka

Junichi Nishimoto

Seiichi Nagata

Katuhiro Norisue

Shuji Ikeda

Kunio Uchiyama

Masayuki Kojima

Yasuko Yoshida

Norio Nakagawa

Mitsuyuki Kimura

Kenji Shiozawa

Motoi Ichihashi

Masakazu Nishibori

Hiroshi Maruyama

Naotoshi Nishioka

Hiroyuki Mizuno

Yusuke Kanno

Tetsuya Yamada

Makoto Saen

Itaru Nonomura

Masafumi Onouchi

Makoto Mizoguchi

Tsuyoshi Koike

Koji Nll

A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA, WLB, WLB, WLA, WLA. Further, a pitch dbetween WLA-WLA and between WLB-WLB is made smaller than a pitch dbetween WLA-WLB. As such, the word lines of an identical port are disposed at the pitch don one of both sides of a certain word line and the word lines of different ports are disposed at the pitch don the other.

Semiconductor device having multiport memory

A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.

Semiconductor device including memory cell array with transistors disposed in different active regions

A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

Semiconductor integrated circuit device and system

Semiconductor device including memory cell array and power supply region

Semiconductor device including memory cell with transistors disposed in different active regions

Semiconductor integrated circuit device and system with memory cell array

The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

Semiconductor integrated circuit device

Growing community of inventors

Kodaira, Japan

Yasuhisa Shimazaki