International Business Machines Corporation

Freescale Semiconductor,inc.

Yaping Zhou

Paul Marian Harvey

Roger Donell Weekly

Chu-Chung Lee

Wolfgang Sauter

Douglas Oliver Powell

Colm Brian O'Reilly

Samuel Wynne Yang

Sang Hoo Dhong

Perry H Pelley

Brian King Flachs

Brad William Michael

Makoto Aikawa

Peter R Harper

Tu-Anh N Tran

Sheila F Chopin

Susan H Downey

Paul Marlan Harvey

Alan H Woosley

Bennett Joiner

Ben W Herberg

A device and/or apparatus having plated through holes (PTHs) which are coated to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.

Reducing impedance discontinuity in packages

An improved system and method for assigning power and ground pins and single ended or differential signal pairs for a ball grid array semiconductor package. In certain embodiments, the system uses a hexagonal pattern where the grid may be represented by a multiplicity of nested hexagonal patterns.

Ball grid array with improved single-ended and differential signal performance

A method, system and apparatus for coating plated through holes (PTHs) to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.

Method and apparatus to reduce impedance discontinuity in packages

A system to improve core package connections may include ball grid array pads, and a ball grid array. The system may also include connection members of the ball grid array conductively connected to respective ball grid array pads. The system may further include magnetic underfill positioned adjacent at least some of the connection members and respective ball grid array pads to increase respective connection members' inductance.

System to improve coreless package connections

A method and system for reducing the noise level of a power supply system with the implementation of a voltage controlled decoupling capacitor in an electrical circuit. Voltage variations of the power supply caused by switching currents are detected by a voltage sensor control circuit. The voltage sensor circuit compares a stable reference voltage with the varying voltage level of the power supply in order to generate a sensor control voltage. When applied to the decoupling capacitor, the control voltage adjusts the capacitance of the voltage controlled capacitor. The adjusted capacitance allows the voltage controlled decoupling capacitor to compensate for the effects of the voltage variations by supplying an increased quantity of charge to various circuit components. Thus, the voltage controlled capacitor is able to efficiently reduce noise within the power supply system.

Voltage controlled on-chip decoupling capacitance to mitigate power supply noise

A semiconductor package uses various forms of conductive traces that connect to die bond pads via bond wires. In one form, adjacent bond wires are intentionally crossed around midpoints thereof to reduce self-inductance of the conductors and to minimize self-inductance. In another form, bond wires associated with bond pads having intervening, unrelated bond pads are crossed. Additionally, conductive traces are divided into separate sections and electrically connected by crossed jumper wires or bond wires. Any number of separate sections may be formed for each trace, but an even number is preferable. In another form, one trace is continuous and divides a second trace into two or more sections. The multiple sections are connected by an overlying bond wire. Either insulated or non-insulated bond wire may be used.

Semiconductor package with crossing conductor assembly and method of manufacture

A method for measuring impedance of a microprocessor chip, electronic packaging, and circuit board power supply system by generating a pseudo-impulse current having a width size in the time domain not larger than the inversion of a maximum frequency of interest and obtaining a voltage measurement in a frequency domain of the pseudo-impulse current. The mechanism of the present invention then predicts the normalized Fourier transformation of the current in the frequency domain, wherein the normalized Fourier transformation depends upon a switching charge of the pseudo-impulse current, measures the switching charge of the pseudo-impulse current, obtains a first current measurement at zero frequency using the measured switching charge, and obtains a second current measurement at a frequency of interest using the first current measurement. The mechanism of the present invention then calculates the impedance of the chip/package/board power supply system using the voltage measurement and the second current measurement.

Impedane measurement of chip, package, and board power supply system using pseudo impulse response

An inductive device () is formed above a substrate () having a conductive coil formed around a core (). The coil comprises segments formed from a first plurality of bond wires () and a second plurality of bond wires (). The first plurality of bond wires () extends between the core () and the substrate (). Each of the first plurality of bond wires is coupled to two of a plurality of wire bond pads (). The second plurality of bond wires () extends over the core () and is coupled between two of the plurality of wire bond pads (). A shield () includes a portion that is positioned between the core () and the substrate ().

Inductive device including bond wires

A semiconductor device has a die () overlying and electrically connected to a support structure (), such as a substrate or a lead frame, via a plurality of interconnects. Aggressor interconnects () are noise sources to victim interconnects () carrying sensitive signals. An arrangement of shield interconnects () surround the victim interconnect () in a cage-like structure to significantly block noise from the aggressor interconnect. In one form the shield interconnects are ground or power supply and the victim interconnect may be, for example, a clock signal or an RF signal. The number of shield interconnects and the number of protected victim interconnects varies depending upon design requirements. Either wire bonding or other interconnect technology (e.g. bump) is applicable.

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Austin, TX, United States of America

Yaping Zhou