Taiwan Semiconductor Manufacturing Comp. Ltd.

Realtek Semiconductor Inc.

Yao-Chun Chuang

Chen-Shien Chen

Chen-Cheng Kuo

Chita Chuang

Ming Hung Tseng

Hao-Juin Liu

Li-Hsien Huang

Tsung-Hsien Chiang

Jun He

Jyun-Lin Wu

Ming-Hong Cha

Ching-Wen Hsiao

Yu-Chen Hsu

Shang-Yun Tu

Ching-Pin Lin

Tin-Hao Kuo

Mirng-Ji Lii

Tsung-Shu Lin

Yu-Sheng Lin

Yinlung Lu

Chen-Hua Douglas Yu

Sheng-Yu Wu

Ting-Ting Kuo

Cheng-Chien Li

Min-Feng Ku

Hao Chun Liu

Ching-Yen Lee

Dian-Hau Chen

Chih-Hua Chen

Hsiang-Ku Shen

Chin-Fu Kao

Yuan-Yang Hsiao

Hong-Seng Shue

Tien-Chung Yang

Chang-Chia Huang

Yuan-Jih Chu

Hsiao Ching-Wen

Chen-Nan Chiu

SyuFong Li

Ming Hsuan Tsai

Ming-Fa Chen

Ming-Da Cheng

Chien-Li Kuo

Chien-Hung Chen

Chih-Lin Wang

Hsien-Wen Liu

Shih-Ting Hung

Chia-Wei Chang

Li-Huan Chu

Chien-Chen Li

Yu-Jen Tseng

Wen-Wei Shen

Ru-Ying Huang

Tsung-Yang Hsieh

Yu-Tse Su

Ming-Jhe Du

Hsin-Hsien Lee

Shih-Kang Tien

Hsueh-Lung Cheng

Ju-Min Chen

Hsin-Yun Hu

Cheng Hung Shen

Cheng-Pu Chiu

The present disclosure provides methods and structures to prevent cracks in redistribution layers. A redistribution structure according to the present disclosure includes a first polymer layer disposed over a silicon substrate, a first contact via disposed in the first polymer layer, a second polymer layer disposed over the first contact via, a first redistribution layer including a first conductive pad disposed on the second polymer layer and a second contact via extending through the second polymer layer to physical contact the first contact via, a third polymer layer disposed over the first redistribution layer, a second redistribution layer including a second conductive pad disposed on the third polymer layer and a plurality of third contact vias extending through the third polymer layer to physically contact the first conductive pad. The first conductive pad has at least one opening and the second conductive pad has at least one opening.

Reduction of cracks in redistribution structure

A semiconductor package structure is provided. The semiconductor package structure includes: a die having a frontside and a backside; a first redistribution layer (RDL) structure disposed on the backside of the die; a second RDL structure disposed on and electrically connected to the frontside of the die; a through integrated fan-out via (TIV) disposed lateral to the die and extending to electrically connect the first and the second RDL structures; a molding compound disposed between the first and second RDL structures; an enhancement layer disposed on the second RDL structure; a plurality of pre-solder bumps; and a plurality of solder balls disposed on and electrically connected to the second RDL structure. The enhancement layer includes a plurality of cascaded openings electrically connected to the first RDL structure. Each of the pre-solder bumps is disposed in one of the cascaded openings.

Fan-out package structures with cascaded openings in enhancement layer

An inquirer-side circuit of an automotive Ethernet system includes: a hybrid circuit arranged to operably conduct data communication with a respondent-side circuit through an MDI circuit; a transmitting circuit coupled with a hybrid circuit and arranged to operably generate and provide a transmission signal to the hybrid circuit; a receiving circuit coupled with the hybrid circuit and arranged to operably receive and parse a received signal transmitted from the hybrid circuit to generate a data signal; a processing circuit coupled with the receiving circuit and arranged to operably process the data signal; a physical coding sublayer circuit coupled with the processing circuit and arranged to operably conduct a physical coding operation to control the operations of the transmitting circuit; and an echo cancellation circuit coupled between the transmitting circuit and the receiving circuit, and arranged to operably generate an echo cancellation signal.

Inquirer-side circuit supporting asymmetry data mode

An inquirer-side circuit of an automotive Ethernet system includes: a hybrid circuit arranged to operably couple with an MDI circuit to conduct data communication with a respondent-side circuit; a transmitting circuit coupled with a hybrid circuit and arranged to operably generate and provide a transmission signal to the hybrid circuit; a receiving circuit coupled with the hybrid circuit and arranged to operably receive and parse a received signal transmitted from the hybrid circuit to generate a data signal; a processing circuit coupled with the receiving circuit and arranged to operably process the data signal; a physical coding sublayer circuit coupled with the processing circuit and arranged to operably conduct a physical coding operation according to the instruction of the processing circuit to control the operations of the transmitting circuit; and an echo cancellation circuit coupled between the transmitting circuit and the receiving circuit.

Inquirer-side circuit capable of operating in asymmetry data mode

An embodiment interfacial bonding test structure may include a first substrate having a first planar surface, a second substrate having a second planar surface that is parallel to the first planar surface, a first semiconductor die, and a second semiconductor die, each semiconductor die bonded between the first substrate and the second substrate thereby forming a sandwich structure. The first semiconductor die and the second semiconductor die may be bonded to the first surface with a first adhesive and may be bonded to the second surface with a second adhesive. The first semiconductor die and the second semiconductor die may be displaced from one another by a first separation along a direction parallel to the first planar surface and the second planar surface. The second substrate may include a notch having an area that overlaps with an area of the first separation in a plan view.

Test structures to determine integrated circuit bonding energies and methods of making and using the same

A first integrated circuit (IC) die includes a first substrate. A second IC die includes a second substrate. At least one of the first substrate or the second substrate has a first surface orientation. The first IC die is spaced apart from the second IC die. A third die electrically interconnects the first IC die to the second IC die. The third die includes a third substrate having a second surface orientation. The second surface orientation is different from the first surface orientation.

Bridge die having different surface orientation than IC dies interconnected by the bridge die

A method of packaging a semiconductor includes: positioning first and second semiconductor dies by one another on a carrier substrate, wherein first and second zones zone are defined with respect to the first die and third and fourth zones are defined with respect to the second die; forming first vias in the first zone, the first vias having a first size; forming second vias in the second zone, the second vias having a second size different from the first; forming third vias in the third zone, the third vias having a third size; forming fourth vias in the fourth zone, the fourth vias having a fourth size different from the third; and electrically connecting the first and second dies with an interconnection die such that electrical signals are exchangeable therebetween.

Integrated fan-out platform and manufacturing method for semiconductor devices

Methods for improving joinder between a surface-mount package and a printed circuit board are disclosed. The warpage at a corner of the surface-mount package and at a corresponding corner of a joint area on the printed circuit board are measured to determine the degree of mismatch. A mini-pad is applied to the corner between the surface-mount package and the joint area on the printed circuit board. The thickness of the mini-pad pushes against the surface-mount package and the printed circuit board, reducing the degree of mismatch below a critical dimension of a ball grid array of the surface-mount package. The surface-mount package can then be soldered to the joint area, reducing or preventing the formation of solder bridges and short circuits.

Methods and systems for improving surface mount joinder

A semiconductor structure includes an interposer having a first planar surface, a set of non-horizontal surfaces having a top periphery that are adjoined to a periphery of the first planar surface, and a frame-shaped surface adjoined to a bottom periphery of the set of non-horizontal surfaces, sidewalls adjoined to the frame-shaped surface, and a second planar surface adjoined to the sidewalls; at least one semiconductor die attached to the interposer through a respective array of solder material portions; and an underfill material portion located between the interposer and the at least one semiconductor die and contacting a portion of the first planar surface.

Interposer including stepped surfaces and methods of forming the same

A semiconductor package includes a substrate and at least one integrated circuit (IC) die. Substrate solder resist has substrate solder resist openings exposing substrate bonding pads of the bonding surface of the substrate, and die solder resist has aligned die solder resist openings exposing die bonding pads of the bonding surface of the IC die. A ball grid array (BGA) electrically connects the die bonding pads with substrate bonding pads via the die solder resist openings and the substrate solder resist openings. The die solder resist openings include a subset A of the die solder resist openings in a region A of the bonding surface of the IC die and a subset B of the die solder resist openings in a region B of the bonding surface of the IC die. The die solder resist openings of subset A are larger than those of subset B.

Semiconductor package with ball grid array connection having improved reliability

A chip package and a method of fabricating the same are disclosed. The chip package includes a substrate with a first region, a second region surrounding the first region, and a third region surrounding the second region, a device layer disposed on the substrate, a via layer disposed on the device layer, an interconnect structure disposed on the via layer, and a stress buffer layer with tapered side profiles disposed on the interconnect structure. First and second portions of the via layer above the first and second regions include first and second set of vias. First, second, and third portions of the interconnect structure above the first, second, and third regions include conductive lines connected to the devices, a first set of dummy metal lines connected to the second set of vias, and a second set of dummy metal lines.

Delamination control of dielectric layers of integrated circuit chips

Integrated circuit (IC) structures and methods for forming the same are provided. An IC structure according to the present disclosure includes a substrate, an interconnect structure over the substrate, a guard ring structure disposed in the interconnect structure, a via structure vertically extending through the guard ring structure, and a top metal feature disposed directly over and in contact with the guard ring structure and the via structure. The guard ring structure includes a plurality of guard ring layers. Each of the plurality of guard ring layers includes a lower portion and an upper portion disposed over the lower portion. Sidewalls of the lower portions and upper portions of the plurality of guard ring layers facing toward the via structure are substantially vertically aligned to form a smooth inner surface of the guard ring structure.

Guard ring structure

In an embodiment, a method includes attaching a first package component to a first carrier, the first package component comprising: an aluminum pad disposed adjacent to a substrate; a sacrificial pad disposed adjacent to the substrate, the sacrificial pad comprising a major surface opposite the substrate, a protrusion of the sacrificial pad extending from the major surface; and a dielectric bond layer disposed around the aluminum pad and the sacrificial pad; attaching a second carrier to the first package component and the first carrier, the first package component being interposed between the first carrier and the second carrier; removing the first carrier; planarizing the dielectric bond layer to comprise a top surface being coplanar with the protrusion; and etching a portion of the protrusion.

Semiconductor package and method of forming same

Embodiments provide metal features which dissipate heat generated from a laser drilling process for exposing dummy pads through a dielectric layer. Because the dummy pads are coupled to the metal features, the metal features act as a heat dissipation feature to pull heat from the dummy pad. As a result, reduction in heat is achieved at the dummy pad during the laser drilling process.

Heat dissipating features for laser drilling process

An exemplary semiconductor structure includes a device substrate having a first side and a second side. A dielectric layer is disposed over the first side of the device substrate. A through via extends along a first direction through the dielectric layer and through the device substrate from the first side to the second side. The through via has a total length along the first direction and a width along a second direction that is different than the first direction. The total length is a sum of a first length of the through via in the dielectric layer and a second length of the through via in the device substrate. The first length is less than the second length. A guard ring is disposed in the dielectric layer and around the through via.

Through via structure

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Hsin-Chu, Taiwan

Yao-Chun Chuang