International Business Machines Corporation

Globalfoundries Inc.

Yanning Sun

Cheng-Wei Cheng

Amlan Majumdar

Kuen-Ting Shiu

Devendra K Sadana

Effendi Leobandung

Edward William Kiewra

Pranita Kerber

Jack Oon Chu

Renee Tong Mo

Anirban Basu

Uzma B Rana

Ghavam G Shahidi

Kevin K Chan

Jeng-Bang Yau

Sanghoon Lee

Young-Hee Kim

Bahman Hekmatshoartabari

Christian Lavoie

Zhen Zhang

Alessandro Cesare Callegari

Katherina E Babich

Zhihong Chen

Pouya Hashemi

Takashi Ando

Keith E Fogel

Vijay Narayanan

Dechao Guo

Paul Michael Solomon

Chung-Hsun Lin

Steven John Koester

Szu-Lin Cheng

Ryan M Martin

Keun-Ting Shiu

Christine Ouyang Qiqing

A semiconductor device comprises a first layer of a substrate arranged on a second layer of the substrate the second layer of the substrate including a doped III-V semiconductor material barrier layer, a gate stack arranged on a channel region of the first layer of a substrate, a spacer arranged adjacent to the gate stack on the first layer of the substrate, an undoped epitaxially grown III-V semiconductor material region arranged on the second layer of the substrate, and an epitaxially grown source/drain region arranged on the undoped epitaxially grown III-V semiconductor material region, and a portion of the first layer of the substrate.

III-V transistor device with self-aligned doped bottom barrier

The present invention relates generally to semiconductor devices and more particularly, to a method of forming a replacement channel composed of a III-V compound semiconductor material in a doped layer of a III-V compound semiconductor substrate. The replacement channel may be formed by removing a portion of the doped layer located directly below a dummy gate stack that has been removed. A III-V compound semiconductor material may be grown in the removed the portion to form the replacement channel and a gate stack may be formed on the replacement channel.

Low external resistance channels in III-V semiconductor devices

A field effect transistor is provided which includes a plurality of fins, at least a portion of a given fin including a respective source region, and a raised source disposed at least partially on the fins and including III-V material. The field effect transistor further includes a diffusion barrier disposed at least partially on the raised source and including transition metal bonded with silicon or germanium, and a gate stack capacitively coupled at least to the respective source regions of the fins.

III-V MOSFET with self-aligned diffusion barrier

A junction field effect transistor (JFET) comprises an insulating carrier substrate, a base semiconductor substrate formed on the insulating carrier substrate and a gate region formed on the base semiconductor substrate. The gate region forms a junction with the base semiconductor substrate. The JFET further comprises a first source/drain region formed on the base semiconductor substrate and located on a first side of the gate region and a second source/drain region formed on the base semiconductor substrate and located on a second side of the gate region. A gate stack is deposited on the gate region, a first source/drain stack is deposited on the first source/drain region and a second source/drain stack is deposited on the second source/drain region. At least one of the gate stack, first source/drain stack and second source/drain stack overlaps onto another one of the gate stack, first source/drain stack and second source/drain stack.

Self-aligned heterojunction field effect transistor

An electrical device comprising a base semiconductor layer of a silicon including material; a dielectric layer present on the base semiconductor layer; a first III-V semiconductor material area present in a trench in the dielectric layer, wherein a via of the III-V semiconductor material extends from the trench through the dielectric layer into contact with the base semiconductor layer; a second III-V semiconductor material area present in the trench in the dielectric layer wherein the second III-V semiconductor material area does not have a via extending through the dielectric layer into contact with the base semiconductor layer; and a semiconductor device present on the second III-V semiconductor material area, wherein the first III-V semiconductor material area and the second III-V semiconductor material area are separated by a low aspect ratio trench extending to the dielectric layer.

III-V field effect transistor on a dielectric layer

A method of forming a semiconducting material includes depositing a graded buffer on a substrate to form a graded layer of an indium (In) containing III-V material, the In containing III-V material being indium-gallium-arsenic (InGaAs) or indium-aluminum-arsenic (InAlAs) and comprising In in an increasing atomic gradient up to 35 atomic % (at. %) based on total atomic weight of InGa or InAl; and forming a layer of InGaAs on the graded layer, the layer of InGaAs comprising about 25 to about 100 at. % In based on total atomic weight of InGa.

Preparation of low defect density of III-V on Si for device fabrication

A method is presented for forming a diffusion barrier in a field effect transistor with a source. A raised source is formed at least partially on the source with the raised source including III-V material. An interfacial layer is formed at least partially on the raised source with the interfacial layer including silicon or germanium. A metal layer is formed at least partially on the interfacial layer with the metal layer including transition metal. The diffusion barrier is formed at least partially on the raised source with the diffusion barrier layer including transition metal from the metal layer bonded to silicon or germanium from the interfacial layer. Similar processing forms a corresponding diffusion barrier on a raised drain.

A method of forming a semiconductor substrate including a type III-V semiconductor material directly on a dielectric material that includes forming a trench in a dielectric layer, and forming a via within the trench extending from a base of the trench to an exposed upper surface of an underlying semiconductor including substrate. A III-V semiconductor material is formed extending from the exposed upper surface of the semiconductor substrate filling at least a portion of the trench.

Planar III-V field effect transistor (FET) on dielectric layer

A method is presented for forming a diffusion barrier in a field effect transistor with a source. A raised source is formed at least partially on the source with the raised source comprising III-V material. An interfacial layer is formed at least partially on the raised source with the interfacial layer comprising silicon or germanium. A metal layer is formed at least partially on the interfacial layer with the metal layer comprising transition metal. The diffusion barrier is formed at least partially on the raised source with the diffusion barrier layer comprising transition metal from the metal layer bonded to silicon or germanium from the interfacial layer. Similar processing forms a corresponding diffusion barrier on a raised drain.

The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a replacement channel composed of a III-V compound semiconductor material in a doped layer of a III-V compound semiconductor substrate. The replacement channel may be formed by removing a portion of the doped layer located directly below a dummy gate stack that has been removed. A III-V compound semiconductor material may be grown in the removed the portion to form the replacement channel and a gate stack may be formed on the replacement channel.

A method is provided that may include providing a plurality of semiconductor pillars extending from a surface of a substrate, wherein a spacer is present on sidewall surfaces of each semiconductor pillar. A seed hole is then formed in a portion of each spacer that exposes a portion of at least one sidewall surface of each semiconductor pillar. Next, a semiconductor nanowire is epitaxially grown from the exposed portion of the at least one sidewall surface of each semiconductor pillar and entirely through each seed hole. A gate structure is then formed straddling over a channel portion of each semiconductor nanowire.

Semiconductor lateral sidewall growth from a semiconductor pillar

A semiconductor structure containing a high mobility semiconductor channel material, i.e., a III-V semiconductor material, and asymmetrical source/drain regions located on the sidewalls of the high mobility semiconductor channel material is provided. The asymmetrical source/drain regions can aid in improving performance of the resultant device. The source region contains a source-side epitaxial doped semiconductor material, while the drain region contains a drain-side epitaxial doped semiconductor material and an underlying portion of the high mobility semiconductor channel material.

Asymmetric III-V MOSFET on silicon substrate

A method for fabricating a semiconductor device may include receiving a gated substrate comprising a substrate with a channel layer and a gate structure formed thereon, over-etching the channel layer to expose an extension region below the gate structure, epitaxially growing a halo layer on the exposed extension region using a first in-situ dopant and epitaxially growing a source or drain on the halo layer using a second in-situ dopant, wherein the first in-situ dopant and the second in-situ dopant are of opposite doping polarity. Using an opposite doping polarity may provide an energy band barrier for the semiconductor device and reduce leakage current. A corresponding apparatus is also disclosed herein.

Growing community of inventors

Scarsdale, NY, United States of America

Yanning Sun