Taiwan Semiconductor Manufacturing Comp. Ltd.

Yang-Hung Chang

Chih-Ming Ke

Kai-Hsiung Chen

Chun-Ming Hu

Che-Yuan Sun

Weimin Hu

Ching-Pin Kao

The present disclosure provides a system. The system includes a metrology tool configured to collect overlay errors from a patterned substrate; and a controller module coupled to the metrology tool and configured to generate an overlay compensation from the collected overlay errors, wherein the generating of the overlay compensation includes identifying a portion of the overlay errors as a set of outliers, identifying inside the set of outliers overlay errors not due to reticle effects, thereby creating a set of noise, excluding the set of noise from overlay errors, thereby creating a set of filtered overlay errors, and calculating the overlay compensation based on the set of filtered overlay errors.

Noise reduction for overlay control

Defect information obtained from a test wafer is received. The test wafer was fabricated according to an Integrated Circuit (IC) design layout. A plurality of first regions of interest (ROIs) is received based on the defect information. The first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred. A frequency domain analysis is performed for the first ROIs. A wafer defect probability is forecast for the IC design layout based at least in part on the frequency domain analysis.

Forecasting wafer defects using frequency domain analysis

A method includes selecting a group of wafers, each of the wafers having a resist pattern; selecting a group of fields for each of the wafers; selecting one or more points on each of the fields; measuring overlay errors on the resist pattern at locations associated with the one or more points selected on the respective wafers; and generating a combined overlay correction map based on measurements of the overlay errors on the wafers. At least one of the selecting of the group of wafers, the selecting of the group of fields, and the selecting of the one or more points is based on a computer-generated model.

Method and system for overlay control

The present disclosure provides a method. The method includes patterning a substrate by a patterning tool; collecting a plurality of overlay errors from a plurality of fields on the substrate; identifying noise from the plurality of overlay errors by applying a first filtering operation and a second filtering operation that is different from the first filtering operation. The method further includes grouping the plurality of overlay errors that are not identified as noise into a set of filtered overlay errors; calculating an overlay compensation based on the set of filtered overlay errors; and performing a compensation process to the patterning tool according to the overlay compensation.

A method for overlay monitoring and control is introduced in the present disclosure. The method includes selecting a group of patterned wafers from a lot using a wafer selection model; selecting a group of fields for each of the selected group of patterned wafers using a field selection model; selecting at least one point in each of the selected group of fields using a point selection model; measuring overlay errors of the selected at least one point on a selected wafer; forming an overlay correction map using the measured overlay errors on the selected wafer; and generating a combined overlay correction map using the overlay correction map of each selected wafer in the lot.

Defect information obtained from a test wafer is received. The test wafer was fabricated according to an Integrated. Circuit (IC) design layout. A plurality of first regions of interest (ROIs) is received based on the defect information. The first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred. A frequency domain analysis is performed for the first ROIs. A wafer defect probability is forecast for the IC design layout based at least in part on the frequency domain analysis.

The present disclosure provides methods and systems for providing a similarity index in semiconductor process control. One of the methods disclosed herein is a method for semiconductor fabrication process control. The method includes steps of receiving a first semiconductor device wafer and receiving a second semiconductor device wafer. The method also includes a step of collecting metrology data from the first and second semiconductor device wafers. The metrology data includes a first set of vectors associated with the first semiconductor device wafer and a second set of vectors associated with the second semiconductor device wafer. The method includes determining a similarity index based in part on a similarity index value between a first vector from the first set of vectors and a second vector from the second set of vectors and continuing to process additional wafers under current parameters when the similarity index is above a threshold value.

Systems and methods for similarity-based semiconductor process control

A method for overlay monitoring and control is introduced in the present disclosure. The method comprises forming resist patterns on one or more wafers in a lot by an exposing tool; selecting a group of patterned wafers in the lot using a wafer selection model; selecting a group of fields for each of the selected group of patterned wafers using a field selection model; selecting at least one point in each of the selected group of fields using a point selection model; measuring overlay errors of the selected at least one point on a selected wafer; forming an overlay correction map using the measured overlay errors on the selected wafer; and generating a combined overlay correction map using the overlay correction map of each selected wafer in the lot.

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Taipei, Taiwan

Yang-Hung Chang