Intel Corporation

Yang Guo

Robert M Nickerson

Nisha Ananthakrishnan

Amram Eitan

Purushotham Kaushik Muthur Srinath

Shripad Gokhale

Elizabeth Nofen

John Decker

Hsin-Yu Li

Nick Ross

Wei Ey Li

Edvin Cetegen

Christopher L Rumer

Xavier Francois Brun

Vipul V Mehta

Shan Zhong

Ziyin Lin

Hsin-Wei Wang

Soud Choudhury

Ifeanyi Okafor

Nai-Yuan Liu

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.

Microelectronics package comprising a package-on-package (PoP) architecture with inkjet barrier material for controlling bondline thickness and PoP adhesive keep out zone

Microelectronics package comprising a package-on-package (PoP) architecture with inkjet barrier material for controlling bondline thickness and pop adhesive keep out zone

Microelectronics package comprising a package-on-package (POP) architecture with inkjet barrier material for controlling bondline thickness and POP adhesive keep out zone

An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure.

Barrier structures for underfill containment

Growing community of inventors

Chandler, AZ, United States of America

Yang Guo