Taiwan Semiconductor Manufacturing Comp. Ltd.

Yang-Cheng Wu

Huan-Just Lin

Yu-Lien Huang

Huang-Ming Chen

Tsai-Chun Li

Cheng-Hua Yang

Wen-Kuo Hsieh

Yun-Hua Chen

In an embodiment, a method includes: depositing a protective layer on a source/drain region and a gate mask, the gate mask disposed on a gate structure, the gate structure disposed on a channel region of a substrate, the channel region adjoining the source/drain region; etching an opening through the protective layer, the opening exposing the source/drain region; depositing a metal in the opening and on the protective layer; annealing the metal to form a metal-semiconductor alloy region on the source/drain region; and removing residue of the metal from the opening with a cleaning process, the protective layer covering the gate mask during the cleaning process.

Transistor source/drain contacts and methods of forming the same

Embodiments of the present disclosure may be used for patterning a layer in a 5 nm node or beyond fabrication to achieve an end-to-end distance below 35 nm. Compared to the state of the art technology, embodiments of the present disclosure reduce cycle time and cost of production from three lithographic processes and four etching processes to one lithographic process and three etch processes.

Methods for controlling an end-to-end distance in semiconductor device

Growing community of inventors

Hsinchu, Taiwan

Yang-Cheng Wu