International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. 2 LLC

Yanfeng Wang

Dechao Guo

Gan Wang

Keith Kwong Hon Wong

Xin Ru Wang

Brian Joseph Greene

Eduard Albert Cartier

Jun Yuan

Yue Liang

Qingqing Liang

Wilfried Haensch

Shu-Jen Han

Chengwen Pei

Chung-Hsun Lin

Shreesh Narasimha

Zhengwen O Li

William K Henson

Randolph F Knarr

Jian Yu

Maryjane Brodsky

Huilong Zhu

Effendi Leobandung

Michael Patrick Chudzik

Sufi Zafar

Jinping Liu

Fen Chen

Philip Joseph Oldiges

Joseph Francis Shepard, Jr

Sunfei Fang

Edward P Maciejewski

Steven Erik Steen

Daewon Yang

Min Dai

Chen Shi

Jeffrey P Gambino

Takashi Ando

Chun-chen Yeh

Zhong-Xiang He

Timothy Dooling Sullivan

Tze-Chiang Chen

Siddarth A Krishnan

Kwong Hon Wong

Huajie Chen

Shahab Siddiqui

Darsen D Lu

Ming Cai

Roger Aime Dufresne

Liyang Song

In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor.

Replacement gate MOSFET with a high performance gate electrode

A device structure for detecting partial pressure of oxygen in blood includes a semiconductor substrate including a source region and a drain region. A multi-layer gate structure is formed on the semiconductor substrate. The multi-layer gate structure includes an oxide layer formed over the semiconductor substrate, a high-k layer formed over the oxide layer, a metal gate layer formed over the high-k layer, and a polysilicon layer formed over the metal gate layer. A receiving area holds a blood sample in contact with the multi-layer gate structure. The high-k layer is exposed to contact the blood sample in the receiving area.

High-k metal gate device structure for human blood gas sensing

A method of manufacturing a semiconductor device is disclosed. A p-type substrate is doped to form an N-well in a selected portion of a p-type substrate adjacent an anode region of the substrate. A p-type doped region is formed in the anode region of the p-type substrate. The p-type doped region and the N-well form a p-n junction.

Partially-blocked well implant to improve diode ideality with SiGe anode

A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1&#xd7;10atoms/cmto 1&#xd7;10atoms/cmis present at an interface between the high-k gate dielectric of the gate structure for the n-type semiconductor device and the semiconductor substrate. Methods of forming the aforementioned device are also disclosed.

Work function adjustment by carbon implant in semiconductor devices including gate structure

FinFET structures and methods of manufacturing the FinFET structures are disclosed. The method includes performing an oxygen anneal process on a gate stack of a FinFET structure to induce Vt shift. The oxygen anneal process is performed after sidewall pull down and post silicide.

FinFET structure and method to adjust threshold voltage in a FinFET structure

A semiconductor device includes a semiconductor-on-insulator (SOI) substrate having a bulk substrate layer, an active semiconductor layer, and a buried insulator layer interposed between the bulk substrate layer and the active semiconductor layer. A first source/drain (S/D) region includes a first stand-alone butting implant having a first butting width. A second S/D region includes a second stand-alone butting implant having a second butting width. A gate well-region is interposed between the first and second S/D regions. The gate well-region has a gate width that is greater than the first and second butting widths.

Semiconductor-on-insulator device including stand-alone well implant to provide junction butting

Embodiments include methods of forming an nFET-tuned gate dielectric and a pFET-tuned gate dielectric. Methods may include forming a high-k layer above a substrate having a pFET region and an nFET region, forming a first sacrificial layer, a pFET work-function metal layer, and a second sacrificial layer above the first high-k layer in the pFET region, and an nFET work-function metal layer above the first high-k layer in the nFET region and above the second sacrificial layer in the pFET region. The first high-k layer then may be annealed to form an nFET gate dielectric layer in the nFET region and a pFET gate dielectric layer in the pFET region. The first high-k layer may be annealed in the presence of a nitrogen source to cause atoms from the nitrogen source to diffuse into the first high-k layer in the nFET region.

Concurrently forming nFET and pFET gate dielectric layers

A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.

Threshold voltage adjustment for thin body MOSFETs

A finFET and method of fabrication are disclosed. A sacrificial layer is formed on a bulk semiconductor substrate. A top semiconductor layer (such as silicon) is disposed on the sacrificial layer. The bulk semiconductor substrate is recessed in the area adjacent to the transistor gate and a stressor layer is formed in the recessed area. The sacrificial layer is selectively removed and replaced with an insulator, such as a flowable oxide. The insulator provides isolation between the transistor channel and the bulk substrate without the use of dopants.

Method and structure for dielectric isolation in a fin field effect transistor

A composite high dielectric constant (high-k) gate dielectric includes a stack of a doped high-k gate dielectric and an undoped high-k gate dielectric. The doped high-k gate dielectric can be formed by providing a stack of a first high-k dielectric material layer and a dopant metal layer and annealing the stack to induce the diffusion of the dopant metal into the first high-k dielectric material layer. The undoped high-k gate dielectric is formed by subsequently depositing a second high-k dielectric material layer. The composite high-k gate dielectric can provide an increased gate-leakage oxide thickness without increasing inversion oxide thickness.

Composite high-k gate dielectric stack for reducing gate leakage

An on-chip poly-to-contact process monitoring and reliability evaluation system and method of use are provided. A method includes determining a breakdown electrical field of each of one or more shallow trench isolation (STI) measurement structures corresponding to respective one or more original semiconductor structures. The method further includes determining a breakdown voltage of each of one or more substrate measurement structures corresponding to the respective one or more original semiconductor structures. The method further includes determining a space between a gate and a contact of each of the one or more original semiconductor structures based on the determined breakdown electrical field and the determined breakdown voltage.

On-chip poly-to-contact process monitoring and reliability evaluation system and method of use

Growing community of inventors

Fishkill, NY, United States of America

Yanfeng Wang