Applied Materials, Inc.

Asml Netherlands B.v.

Yana Cheng

Yong Cao

Mehul B Naik

He Ren

Xianmin Tang

Chenxi Lin

Youping Zhang

Yi Zou

Srinivas Guggilla

Weifeng Ye

Sree Rangasai V Kesapragada

Cyrus Emil Tabery

Deenesh Padhi

Maxime Philippe Frederic Genin

Simon Philip Spencer Hastings

Boris Menchtchikov

David P Thompson

Paul F Ma

Rongjun Wang

Mei-Yee Shek

Kevin Vincent Moraes

Thanh X Nguyen

Davit Harutyunyan

Wim Tjibbo Tel

Hakki Ergün Cekli

Weimin Zeng

Daniel Lee Diehl

William R Johanson

Chi Hong Ching

Roy Werkman

Daan Maurits Slotboom

Alexander Jansen

David Frans Simon Deckers

Abraham Slachter

Sree Rangasai Kesapragada

Tzu-Chao Chen

Randal Dean Schmieding

Matthijs Cox

Samee Ur Rehman

Vadim Yourievich Timoshkov

Koen Wilhelmus Cornelis Adrianus Van Der Straten

Nicolaas Petrus Marcus Brantjes

Zhefeng Li

Jeffrey Thomas Ziebarth

Maxim Philippe Frederic Genin

A method for predicting yield relating to a process of manufacturing semiconductor devices on a substrate, the method including: obtaining a trained first model which translates modeled parameters into a yield parameter, the modeled parameters including: a) a geometrical parameter associated with one or more selected from: a geometric characteristic, dimension or position of a device element manufactured by the process and b) a trained free parameter; obtaining process parameter data including data regarding a process parameter characterizing the process; converting the process parameter data into values of the geometrical parameter; and predicting the yield parameter using the trained first model and the values of the geometrical parameter.

Method to predict yield of a device manufacturing process

A method for analyzing a process, the method including obtaining a multi-dimensional probability density function representing an expected distribution of values for a plurality of process parameters; obtaining a performance function relating values of the process parameters to a performance metric of the process; and using the performance function to map the probability density function to a performance probability function having the process parameters as arguments.

Method of manufacturing devices

A method for determining a correction relating to a performance metric of a semiconductor manufacturing process, the method including: obtaining a set of pre-process metrology data; processing the set of pre-process metrology data by decomposing the pre-process metrology data into one or more components which: a) correlate to the performance metric; or b) are at least partially correctable by a control process which is part of the semiconductor manufacturing process; and applying a trained model to the processed set of pre-process metrology data to determine the correction for the semiconductor manufacturing process.

Method for controlling a manufacturing process and associated apparatuses

A method for determining a root cause affecting yield in a process for manufacturing devices on a substrate, the method including: obtaining yield distribution data including a distribution of a yield parameter across the substrate or part thereof; obtaining sets of metrology data, each set including a spatial variation of a process parameter over the substrate or part thereof corresponding to a different layer of the substrate; comparing the yield distribution data and metrology data based on a similarity metric describing a spatial similarity between the yield distribution data and an individual set out of the sets of the metrology data; and determining a first similar set of metrology data out of the sets of metrology data, being the first set of metrology data in terms of processing order for the corresponding layers, which is determined to be similar to the yield distribution data.

Method for determining root cause affecting yield in a semiconductor manufacturing process

A method for determining a correction for an apparatus used in a process of patterning substrates, the method including: obtaining a group structure associated with a processing history and/or similarity in fingerprint of to be processed substrates; obtaining metrology data associated with a plurality of groups within the group structure, wherein the metrology data is correlated between the groups; and determining the correction for a group out of the plurality of groups by applying a model to the metrology data, the model including at least a group-specific correction component and a common correction component.

Method for determining corrections for lithographic apparatus

A movable substrate support with a top surface for holding a substrate, when present, is used in conjunction with a cover ring that is stationary to adjust for a shadow effect to control substrate edge uniformity during deposition processes. The cover ring is held stationary by an electrically isolated spacer that engages with a grounded shield in the process volume of a semiconductor process chamber. A controller adjusts the substrate support in response to deposition material on a top surface of the cover ring to maintain the shadow effect and substrate edge uniformity.

Methods and apparatus for substrate edge uniformity

In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.

Methods for depositing dielectric barrier layers and aluminum containing etch stop layers

Methods are disclosed for depositing a thin film of compound material on a substrate. In some embodiments, a method of depositing a layer of compound material on a substrate include: flowing a reactive gas into a plasma processing chamber having a substrate to be sputter deposited disposed therein in opposition to a sputter target comprising a metal; exciting the reactive gas into a reactive gas plasma to react with the sputter target and to form a first layer of compound material thereon; flowing an inert gas into the plasma processing chamber; and exciting the inert gas into a plasma to sputter a second layer of the compound material onto the substrate directly from the first layer of compound material. The cycles of target poisoning and sputtering may be repeated until a compound material layer of appropriate thickness has been formed on the substrate.

Methods for thin film material deposition using reactive plasma-free physical vapor deposition

The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer.

Method to reduce trap-induced capacitance in interconnect dielectric barrier stack

Interconnect structures and methods of formation of such interconnect structures are provided herein. In some embodiments, a method of forming an interconnect includes: depositing a silicon-aluminum oxynitride (SiAlON) layer atop a first layer of a substrate, wherein the first layer comprises a first feature filled with a first conductive material; depositing a dielectric layer over the silicon-aluminum oxynitride (SiAlON) layer; and forming a second feature in the dielectric layer and the silicon-aluminum oxynitride (SiAlON) layer to expose the first conductive material.

Interconnect structures and methods of formation

In some embodiments a method of processing a substrate disposed atop a substrate support in a physical vapor deposition process chamber includes: (a) depositing a dielectric layer to a first thickness atop a first surface of the substrate via a physical vapor deposition process; (b) providing a first plasma forming gas to a processing region of the physical vapor deposition process chamber, wherein the first plasma forming gas comprises hydrogen but not carbon; (c) providing a first amount of bias power to a substrate support to form a first plasma from the first plasma forming gas within the processing region of the physical vapor deposition process chamber; (d) exposing the dielectric layer to the first plasma; and (e) repeating (a)-(d) to deposit the dielectric film to a final thickness.

Methods for depositing dielectric films via physical vapor deposition processes

An interconnect structure for use in semiconductor devices and a method for fabricating the same is described. The method includes positioning a substrate in a vacuum processing chamber. The substrate has an exposed copper surface and an exposed low-k dielectric surface. A metal layer is formed over the copper surface but not over the low-k dielectric surface. A metal-based dielectric layer is formed over the metal layer and the low-k dielectric layer.

Dielectric/metal barrier integration to prevent copper diffusion

Methods for forming a passivation protection structure on a metal line layer formed in an insulating material in an interconnection structure are provided. In one embodiment, a method for forming passivation protection on a metal line in an interconnection structure for semiconductor devices includes selectively forming a metal capping layer on a metal line bounded by a dielectric bulk insulating layer in an interconnection structure formed on a substrate in a processing chamber incorporated in a multi-chamber processing system, in-situ forming a barrier layer on the substrate in the processing chamber; wherein the barrier layer is a metal dielectric layer, and forming a dielectric capping layer on the barrier layer in the multi-chamber processing system.

Methods for forming passivation protection for an interconnection structure

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San Jose, CA, United States of America

Yana Cheng