Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor Manufacturing International (beijing) Corporation

Shanghai Ic R&d Center Co., Ltd

Yan Yan

Jun Yang

Pengfei Wang

Hao Deng

Tao Zhou

Hao Fu

Jiebin Duan

Lingyi Guo

Hongxia Sun

Xueru Yu

Xiucui Wang

Liren Li

Tingting Peng

Chen Li

Bowen Xu

The present invention disclosures a critical dimension error analysis method, comprising: S: performing lithography processes on a wafer, measuring the critical dimension (CD) values of the test points in each of the fields respectively; M and N are integers greater than 1; S: removing extreme outliers from the critical dimension (CD) values; S: rebuilding remaining CD values by a reconstruction model fitting method, and obtaining rebuilt critical dimension (CD″) values, according to relative error between CD″ and CD, dividing the rebuilt critical dimension (CD″) values into scenes and the number of the scenes is A; S: calculating components and corresponding residuals of the test points in each of the scenes under a reference system corresponding to a correction model by parameter estimation; S: modifying machine parameters and masks by the correction model according to above calculation results. The present invention uses an outer limit to remove extreme outliers, so as to analyze a critical dimension error during a lithography process quickly and accurately.

Critical dimension error analysis method

In accordance with various embodiments of the disclosed subject matter, a shallow trench isolation structure and a fabricating method thereof are provided. The method for forming the shallow trench isolation structure may include: providing a semiconductor substrate; forming a shallow trench in the semiconductor substrate; forming a first insulating layer on a surface of the semiconductor substrate and in the shallow trench, a portion of the first insulating layer in the shallow trench includes an opening; etching the first insulating layer to increase a width of the opening; after etching the first insulating layer, performing a plasma treatment to an exposed surface of the first insulating layer; after the plasma treatment, cleaning the surface of the first insulating layer; and after cleaning the surface of the first insulating layer, filling a second insulating layer into the shallow trench.

Shallow trench isolation structure and fabricating method thereof

A method for forming an isolation member in a trench of a substrate may include the following steps: performing a first deposition process to form a first isolation material set, which is at least partially positioned in the trench; partially removing the first isolation material set, such that a remaining portion of the first isolation material set remains in the trench; after the first isolation material set has been partially removed, performing a fluorine-reduction process on at least the remaining portion of the first isolation material set; after the fluorine-reduction process, performing a second deposition process to form a second isolation material set, which is at least partially positioned in the trench, wherein the second isolation material set includes the remaining portion of the first isolation material set; and processing the second isolation material set for forming the isolation member.

Method for forming isolation member in trench of semiconductor substrate

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Shanghai, China

Yan Yan