Csmc Technologies Fab2 Co., Ltd.

Southeast University

Chinese Academy of Forestry

Yan Gu

Sen Zhang

Shikang Cheng

Longxing Shi

Weifeng Sun

Jing Wang

Long Zhang

Jie Ma

Wei Su

Jing Zhu

Xingdi Li

Jinli Gong

An insulated gate bipolar transistor, comprising an anode second conductivity-type region and an anode first conductivity-type region provided on a drift region; the anode first conductivity-type region comprises a first region and a second region, and the anode second conductivity-type region comprises a third region and a fourth region, the dopant concentration of the first region being less than that of the second region, the dopant concentration of the third region being less than that of the fourth region, the third region being provided between the fourth region and a body region, the first region being provided below the fourth region, and the second region being provided below the third region and located between the first region and the body region.

Insulated gate bipolar transistor

A transient voltage suppression device includes: a substrate; a first conductive type well region including a first well and a second well; a second conductive type well region including a third well and a fourth well, the third well being disposed between the first well and the second well so as to isolate the first well and the second well, and the second well being disposed between the third well and the fourth well; a zener diode active region; a first doped region, provided in the first well; a second doped region, provided in the first well; a third doped region, provided in the second well; a fourth doped region, provided in the second well; a fifth doped region, provided in the zener diode active region; and a sixth doped region, provided in the zener diode active region.

Transient voltage suppression device and manufacturing method therefor

A transient voltage suppression device and a manufacturing method therefor, the transient voltage suppression device including: a substrate, a first conductivity type well region and a second conductivity type well region disposed in the substrate. The first conductivity type well region includes a first well, a second well, and a third well. The second conductivity type well region includes a fourth well that isolates the first well from the second well, and a fifth well that isolates the second well from the third well. The device further includes a Zener diode well region provided in the first well, a first doped region provided in the Zener diode well region, a second doped region provided in the Zener diode well region, a third doped region provided in the second well, a fourth doped region provided in the third well, and a fifth doped region provided in the third well.

A TVS device and a manufacturing method therefor. The TVS device comprises: a first doping type semiconductor substrate (); a second doping type deep well I (), a second doping type deep well II (), and a first doping type deep well () provided on the semiconductor substrate; a second doping type heavily doped region I () provided in the second doping type deep well I (); a first doping type well region () and a first doping type heavily doped region I () provided in the second doping type deep well II (); a first doping type heavily doped region II () and a second doping type heavily doped region II () provided in the first doping type deep well (); a second doping type heavily doped region III () located in the first doping type well region () and the second doping type deep well II (); and a first doping type doped region () provided in the first doping type well region ().

TVS device and manufacturing method therefor

A trench gate depletion-type VDMOS device and a method for manufacturing the same are disclosed. The device comprises a drain region; a trench gate including a gate insulating layer on an inner wall of a trench and a gate electrode filled in the trench and surrounded by the gate insulating layer; a channel region located around the gate insulating layer; a well region located on both sides of the trench gate; a source regions located within the well region; a drift region located between the well region and the drain region; a second conductive-type doped region located between the channel region and the drain region; and a first conductive-type doped region located on both sides of the second conductive-type doped region and located between the drift region and the drain region.

Trench gate depletion mode VDMOS device and method for manufacturing the same

The present application provides an integrated semiconductor device and an electronic apparatus, comprising a semiconductor substrate and a first doped epitaxial layer having a first region, a second region, and a third region; a partition structure is arranged in the third region; the first region is formed having at least two second doped deep wells, and the second region is formed having at least two second doped deep wells; a dielectric island partially covers a region between two adjacent doped deep wells in the first region and second region; a gate structure covers the dielectric island; a first doped source region is located on the two sides of the gate structure, and a first doped source region located in the same second doped deep well is separated; a first doped trench is located on the two sides of the dielectric island in the first region, and extends laterally to the first doped source region.

Integrated semiconductor device and electronic apparatus

A manufacturing method for a semiconductor device, and an integrated semiconductor device. The manufacturing method comprises: on a semiconductor substrate, forming an epitaxial layer having a first region, a second region, and a third region; forming at least one groove in the third region, forming at least two second doping deep traps in the first region, and forming at least two second doping deep traps in the second region; forming a first dielectric island between the second doping deep traps and forming a second dielectric island on the second doping deep traps; forming a first doping groove at both sides of the first dielectric island in the first region; forming a gate structure on the first dielectric island; forming an isolated first doping source region using the second dielectric island as a mask.

Manufacturing method for semiconductor device and integrated semiconductor device

A transient voltage suppression device includes a substrate; a first conductivity type well region disposed in the substrate and comprising a first well and a second well; a third well disposed on the substrate, a bottom part of the third well extending to the substrate; a fourth well disposed in the first well; a first doped region disposed in the second well; a second doped region disposed in the third well; a third doped region disposed in the fourth well; a fourth doped region disposed in the fourth well; a fifth doped region extending from inside of the fourth well to the outside of the fourth well, a portion located outside the fourth well being located in the first well; a sixth doped region disposed in the first well; a seventh doped region disposed below the fifth doped region and in the first well.

A method for manufacturing a semiconductor device and an integrated semiconductor device, said method comprising: providing an epitaxial layer having a first region and a second region, forming, in the first region, at least two second doping-type deep wells, and forming, in the second region, at least two second doping-type deep wells; forming a first dielectric island between the second doping-type deep wells and forming a second dielectric island on the second doping-type deep wells; forming a first doping-type trench on two sides of the first dielectric island in the first region; forming a gate structure on the first dielectric island; and forming a separated first doping-type source region by using the second dielectric island as a mask, the first doping-type trench extending, in the first region, transversally to the first doping-type source region.

Method for manufacturing semiconductor device and integrated semiconductor device

A device integrated with a junction field-effect transistor, the device is divided into a JFET region and a power device area, and the device includes: a drain () having a first conduction type; and a first conduction type region () disposed on a front face of the drain; the JFET region further includes: a JFET source () having a first conduction type; a first well () having a second conduction type; a metal electrode () formed on the JFET source (), which is in contact with the JFET source (); a JFET metal gate () disposed on the first well () at both sides of the JFET source (); and a first clamping region () located below the JFET metal gate () and within the first well ().

Device integrated with junction field effect transistor and method for manufacturing the same

A device integrated with JFET, the device is divided into a JFET region and a power device region, and the device includes: a drain () with a first conduction type; and a first conduction type region disposed on a front surface of the drain (); the JFET region includes: a first well () with a second conduction type and formed in the first conduction type region; a second well () with a second conduction type and formed in the first conduction type region; a JFET source () with the first conduction type; a metal electrode formed on the JFET source (), which is in contact with the JFET source (); and a second conduction type buried layer () formed under the JFET source () and the second well ().

A device integrated with a depletion-mode junction field-effect transistor and a method for manufacturing the device. The device includes: a well region, which is of a second conduction type and formed within a first conduction region (); a JFET source (), which is of a first conduction type and formed within the well region; a metal electrode () of the JFET sources formed on the JFET sources (), which is in contact with the JFET sources (); a lateral channel region (), which is of the first conduction type and formed between two adjacent JFET sources (), while two ends thereof are in contact with the two adjacent JFET sources (); and a JFET metal gate () formed on the well region.

Device integrated with depletion-mode junction fielf-effect transistor and method for manufacturing the same

A lateral insulated gate bipolar transistor, comprising: a substrate (), having a first conductivity type; an insulating layer (), formed on the substrate (); an epitaxial layer (), having a second conductivity type and formed on the insulating layer (); a field oxide layer (), formed on the epitaxial layer (); a first well (), having the first conductivity type; a plurality of gate trench structures (); second source doped regions (), having the second conductivity type; first source doped regions (), having the first conductivity type; a second well (), having the second conductivity type; a first drain doped region (), having the first conductivity type and formed on a surface layer of the second well (); gate lead-out ends (); a source lead-out end (); a drain lead-out end ().

Lateral insulated gate bipolar transistor

Disclosed is a process for preparing isopimaric acid, comprising the following steps: First step: dissolving thermally isomerized rosin in acetone, adding in drops a solution of isobutanolamine in acetone to form a precipitate, standing, filtering, washing with ethanol, and drying to obtain crude ammonium salt of isopimaric acid; recrystallizing the crude ammonium salt of isopimaric acid according to multi-recrystallization, and drying to obtain purified crystal of ammonium salt of isopimaric acid; Second step: dissolving the purified crystal of ammonium salt of isopimaric acid obtained in the first step in ether, adding hydrochloric acid in portions until the crystal of ammonium salt of isopimaric acid disappears, removing a water layer and washing the ether layer with water to neutral, evaporating the ether, dissolving the residue in acetone, adding water slowly into the solution dropwise until crystals cease to grow, then filtering and drying to obtain purified isopimaric acid.

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Jiangsu, China

Yan Gu