Globalfoundries Inc.

Globalfoundries U.S. Inc.

Globaleoundries U.S. Inc.

Xusheng Kevin Wu

Haigou Huang

Min-Hwa Chi

Changyong Xiao

Hui Zang

John H Zhang

Jianwei Peng

Wanxun He

Hong Yu

Yi Qi

Chengwen Pei

Jiehui Shu

Sipeng Gu

Jin Ping Liu

Hongliang Shen

Ziyan Xu

Haiting Wang

Hsien-Ching Lo

Jinsheng Gao

Ruilong Xie

Manfred Eller

Zhenyu Hu

Xiang Hu

Edmund Kenneth Banghart

Jeffrey Chee

Laertis Economikos

Yanxiang Liu

Guoxiang Ning

Daniel J Jaeger

Randy W Mann

George Robert Mulfinger

David Paul Brunco

Bingwu Liu

Paul Willard Ackmann

Xintuo Dai

Xinyuan Dou

Yuping Ren

Chin Teong Lim

Wei Zhao

Xiaodong Yang

Lun Zhao

Byoung-Gi Min

Dongil Choi

Wenhe Lin

Chanro Park

Ajey Poovannummoottil Jacob

Julien Frougier

Qizhi Liu

Xiuyu Cai

Min Gyu Sung

Hiroaki Niimi

Siva P Adusumilli

Jinping Liu

Steven J Bentley

David Louis Harame

Shesh Mani Pandey

Renata A Camillo-Castillo

Murat Kerem Akarvardar

Sunil Kumar Singh

Qi Zhang

Yong Meng Lee

Steven R Soss

Ravi Prakash Srivastava

Yanping Shen

Michael Vincent Aquilino

Wei Hong

Zhao Lun

Xin Wang

Richard J Carter

Chun Yu Wong

Nigel Graeme Cave

Akshey Sehgal

Tao Han

Teck Jung Tang

Yongjun Shi

Patrick D Carpenter

Hui Zhan

Pei Liu

Wen-Pin Peng

Ashish Kumar Jha

Stan Tsai

Anuj Gupta

Ming Lei

Yan Ping Shen

Weihua Tong

Yue Hu

Guoliang Zhu

Sonia Ghosh

Jie Chen

Alina Vinslava

Konstantin G Korablev

Jeasung Park

Sandeep Puri

Fangyu Wu

Dong-Woon Shin

Wei-Hua Tong

Hongxiang Mo

Jiajun Mao

Wanxum He

Md Khaled Hassan

One illustrative integrated circuit product disclosed herein includes a first final gate structure having a first end surface and a second final gate structure having a second end surface. In this embodiment, the integrated circuit product also includes an insulating gate separation structure positioned between the first and second final gate structures, wherein the first end surface contacts a first side surface of the insulating gate separation structure and the second end surface contacts a second side surface of the insulating gate separation structure. In this embodiment, the insulating gate separation structure has an inverted T-shaped cross-sectional configuration in at least one direction.

IC product comprising a novel insulating gate separation structure for transistor devices

A vertical fin field effect transistor includes a semiconductor fin disposed over a well region and a gate conductor layer disposed over a sidewall of the fin, and extending laterally over a top surface of the well region adjacent to the fin. The extension of the gate conductor over the bottom source/drain effectively increases the channel length of the vertical FinFET device independent of the fin height. A bottom source/drain region is laterally adjacent to the well region such that the portion of the well region covered by the laterally extended gate stack is between the bottom source/drain region and the portion of the well region immediately under the fin. A top source/drain region is located above the fin. The device is operated in circuits by use of electrical contacts to the bottom source/drain, the gate conductor, and the top source/drain.

Method and structure to provide integrated long channel vertical FinFet device

Methods comprising providing a semiconductor substrate; a fin disposed on the semiconductor substrate; a dummy gate disposed over the fin, wherein the dummy gate has a top at a first height above the substrate; and an interlayer dielectric (ILD) disposed over the fin and adjacent to the dummy gate, wherein the ILD has a top at a second height above the substrate, wherein the second height is below the first height; and capping the ILD with a dielectric cap, wherein the dielectric cap has a top at the first height. Systems configured to implement the methods. Semiconductor devices produced by the methods.

Methods, apparatus, and system for reducing gate cut gouging and/or gate height loss in semiconductor devices

In conjunction with a replacement metal gate (RMG) process for forming a fin field effect transistor (FinFET), gate isolation methods and associated structures leverage the formation of distinct narrow and wide gate cut regions in a sacrificial gate. The formation of a narrow gate cut between closely-spaced fins can decrease the extent of etch damage to interlayer dielectric layers located adjacent to the narrow gate cut by delaying the deposition of such dielectric layers until after formation of the narrow gate cut opening. The methods and resulting structures also decrease the propensity for short circuits between later-formed, adjacent gates.

Method of manufacturing finfet devices using narrow and wide gate cut openings in conjunction with a replacement metal gate process

The present disclosure relates to semiconductor structures and, more particularly, to selective shallow trench isolation (STI) fill material for stress engineering in semiconductor structures and methods of manufacture. The structure includes a single diffusion break (SDB) region having at least one shallow trench isolation (STI) region with a stress fill material within a recess of the at least one STI region. The stress fill material imparts a stress on a gate structure adjacent to the at least one STI region.

Selective shallow trench isolation (STI) fill for stress engineering in semiconductor structures

The present disclosure relates to semiconductor structures and, more particularly, to a contact over an active gate structure and methods of manufacture. The structure includes: an active gate structure composed of conductive material located between sidewall material; an upper sidewall material above the sidewall material, the upper sidewall material being different material than the sidewall material; and a contact structure in electrical contact with the conductive material of the active gate structure. The contact structure is located between the sidewall material and between the upper sidewall material.

Contact structures

One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, the sacrificial gate structure comprising a sacrificial gate insulation layer and a multi-layer sacrificial gate electrode structure, removing the sacrificial gate structure to form a replacement gate cavity, and forming a replacement gate structure in the replacement gate cavity.

Methods of forming replacement gate structures on transistor devices

The present disclosure relates to semiconductor structures and, more particularly, to a spacer integration scheme for both NFET and PFET devices and methods of manufacture. The structure includes: a plurality of epitaxial grown fin structures for NFET devices having sidewall spacers of a first dimension; and a plurality epitaxial grown fin structures for PFET devices having sidewall spacers of the first dimension.

Spacer integration scheme for FNET and PFET devices

A semiconductor structure including a source/drain region is disclosed. The source/drain region may include a first epitaxial region along at least one sidewall of the source/drain region having a substantially uniform sidewall thickness. The semiconductor structure may further include a gate structure adjacent and above the source/drain region wherein at least a portion of the first epitaxial region is positioned below a sidewall spacer of the gate structure. A method of forming a source/drain region including a first epitaxial region having a substantially uniform sidewall thickness is disclosed. The method may include forming a trench in a substrate adjacent to a gate structure, forming the first epitaxial region in the trench, forming a spacer material layer on the gate structure and on a portion of the first epitaxial region, and removing a portion of the first epitaxial region using the spacer material layer as a mask.

Epitaxial region for embedded source/drain region having uniform thickness

Structures that include a metal-insulator-metal (MIM) capacitor and methods for fabricating a structure that includes a MIM capacitor. The MIM capacitor includes a first electrode, a second electrode, and a third electrode. A conductive via is arranged in a via opening extending in a vertical direction through at least the first electrode. The first electrode has a surface arranged inside the via opening in a plane transverse to the vertical direction, and the conductive via contacts the first electrode over an area of the surface.

Metal-insulator-metal capacitors with enlarged contact areas

At least one method, apparatus and system disclosed herein involves forming a sigma shaped source/drain lattice. A fin is formed on a semiconductor substrate. A gate region is formed over the fin. In a source region and a drain region adjacent bottom portions of the fin, a first recess cavity is formed in the source region, and a second recess cavity is formed in the drain region. The first and second recess cavities comprise sidewalls formed in an angle relative to a vertical axis. Portions of the first and second recess cavities extend below the fin. In the first recess cavity, a first rare earth oxide layer is formed, and in the second recess cavity, a second rare earth oxide layer is formed.

Methods, apparatus and system for forming sigma shaped source/drain lattice

The present disclosure relates to semiconductor structures and, more particularly, to fin structures with single diffusion break facet improvement using an epitaxial insulator and methods of manufacture. The structure includes: a plurality of fin structures; an insulator material filling a cut between adjacent fin structures of the plurality of fin structures; a metal material (e.g., rare earth oxide or SrTiO) at least partially lining the cut; and an epitaxial source region or epitaxial drain region in at least one of the plurality of fin structures and adjacent to the metal material.

Fins with single diffusion break facet improvement using epitaxial insulator

A composite etch stop layer includes an oxide layer formed over a sacrificial gate structure and a nitride layer formed over the oxide layer. The oxide layer is disposed over only lower portions of the sacrificial gate structure while the nitride layer envelops the oxide layer and is disposed directly over a top surface of the sacrificial gate structure. Sensitivity of the nitride layer to oxidation, such as during the formation of an interlayer dielectric over the composite etch stop layer, is decreased by eliminating the oxide layer from upper portions of the sacrificial gate layer.

Composite contact etch stop layer

Devices and methods of fabricating integrated circuit devices for increasing performance through gate cut last processes are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a plurality of fins, an STI layer, an oxide layer, and a gate material over the oxide layer, the fins extending into the gate material; removing the gate material and the oxide layer; depositing a high k material on a top surface of the STI layer, surrounding the fins; depositing a gate stack over the high k material; filling the top of the device with a gate contact metal; etching a portion of the gate contact metal, the metal gate stack, and the high k material; and filling the portion with an inter-layer dielectric. Also disclosed is an intermediate device formed by the method.

Device for improving performance through gate cut last process

A method of forming a FinFET fin with low-doped and a highly-doped active portions and/or a FinFET fin having tapered sidewalls for Vt tuning and multi-Vt schemes and the resulting device are provided. Embodiments include forming an Si fin, the Si fin having a top active portion and a bottom active portion; forming a hard mask on a top surface of the Si fin; forming an oxide layer on opposite sides of the Si fin; implanting a dopant into the Si fin; recessing the oxide layer to reveal the active top portion of the Si fin; etching the top active portion of the Si fin to form vertical sidewalls; forming a nitride spacer covering each vertical sidewall; recessing the recessed oxide layer to reveal the active bottom portion of the Si fin; and tapering the active bottom portion of the Si fin.

Fin structures and multi-Vt scheme based on tapered fin and method to form

Growing community of inventors

Hopewell Junction, NY, United States of America

Xusheng Kevin Wu