Applied Materials, Inc.

Xumou Xu

Huixiong Dai

Christopher Dennis Bencher

Hui W Chen

Christopher S Ngai

Raymond Hoiman Hung

Michael Duane

Yongmei Chen

Jen Shu

Chorng-Ping Chang

Susie Xiuru Yang

Christopher Siu Wing Ngai

Kenneth MacWilliams

Jiahua Yu

Embodiments of the present invention relate to lithographic processes used in integrated circuit fabrication for improving line edge roughness (LER) and reduced critical dimensions (CD) for lines and/or trenches. Embodiments use the combinations of polarized light lithography, shrink coating processes, and double exposure processes to produce synergetic effects in the formation of trench structures having good resolution, reduced CDs, reduced pitch, and reduced LER in the lines and/or trenches of the patterned interconnect structures.

Line edge roughness reduction and double patterning

Methods to pattern features in a substrate layer by exposing a photoresist layer more than once. In one embodiment, a single reticle may be exposed more than once with an overlay offset implemented between successive exposures to reduce the half pitch of the reticle. In particular embodiments, these methods may be employed to reduce the half pitch of the features printed with 65 nm generation lithography equipment to achieve 45 nm lithography generation CD and pitch performance.

Double exposure patterning with carbonaceous hardmask

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Campbell, CA, United States of America

Xumou Xu