Chartered Semiconductor Manufacturing Ltd (corporation)

Xue Chun Dai

Mei Sheng Zhou

Kwok Keung Paul Ho

Chiew Wah Yap

A method for forming an etched silicon layer. There is first provided a first substrate having formed thereover a first silicon layer. There is then etched the first silicon layer to form an etched first silicon layer while employing a plasma etch method employing a plasma reactor chamber in conjunction with a plasma etchant gas composition which upon plasma activation provides at least one of an active bromine containing etchant species and an active chlorine containing etchant species. Within the plasma etch method: (1) a cleaned plasma reactor chamber is seasoned to provide a seasoned plasma reactor chamber having a seasoning polymer layer formed therein; (2) the first silicon layer is etched to form the etched first silicon layer within the seasoned plasma reactor chamber; and (3) the seasoning polymer layer is cleaned from the seasoned plasma reactor chamber to provide the cleaned plasma reactor chamber after etching the first silicon layer to form the etched first silicon layer within the seasoned plasma reactor chamber, prior to etching a second silicon layer to form an etched second silicon layer formed over a second substrate within the plasma reactor chamber while employing the plasma etch method in accord with (1), (2) and (3).

Plasma etch method for forming plasma etched silicon layer

A method for forming a patterned microelectronic layer. There is first provided a substrate. There is then formed over the substrate a multi-layer stack layer comprising: (1) a first lower microelectronic layer; (2) a second intermediate patterned microelectronic layer formed over the first lower microelectronic layer; and (3) a third upper patterned microelectronic layer formed over the second intermediate patterned microelectronic layer, where the first lower microelectronic layer and the third upper patterned microelectronic layer are susceptible to etching within a first etchant. There is then formed encapsulating the first lower microelectronic layer and at least portion of the second intermediate patterned microelectronic layer while leaving exposed at least a portion of the third upper patterned microelectronic layer an encapsulating layer. There is then etched selectively, while employing a first etch method which employs the first etchant, the third upper patterned microelectronic layer while the first lower microelectronic layer and at least the portion of the second intermediate patterned microelectronic layer are encapsulated with the encapsulating layer. Finally, there is then stripped, while employing a second etch method which employs a second etchant, from the first microelectronic layer and at least the portion of the second intermediate patterned microelectronic layer the encapsulating layer. The method may be employed for stripping from a gate electrode within a field effect transistor (FET) a patterned dielectric cap layer formed upon the gate electrode while not etching a gate dielectric layer upon Which is formed the gate electrode within the field effect transistor (FET).

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Singapore, Singapore

Xue Chun Dai