Nxp Usa, Inc.

Xu Jason Ma

Elie A Maalouf

David Edward Bien

Madan Mohan Reddy Vemula

Mohammad Nizam Kabir

Ngai-Ming Lau

A system includes a reference field effect transistor (FET), wherein the reference FET is a depletion mode transistor, and a bias control circuit. The bias control circuit includes a voltage sensor connected to a drain terminal of the reference FET. The voltage sensor is configured to measure a voltage at the drain terminal of the reference FET as a measured voltage, determine a voltage difference between a reference voltage and the measured voltage, and output the voltage difference at a voltage sensor output terminal. The system includes a translation circuit connected the voltage sensor output terminal. The translation circuit is configured to convert the voltage difference into a negative gate bias voltage, and apply the negative gate bias voltage to a gate terminal of the reference FET.

Bias control circuit for power transistors

A switching device may include an input terminal, an output terminal, a primary switching transistor electrically coupled between the input terminal and the output terminal, and a cascode arrangement electrically coupled between the primary switching transistor and the input terminal. The cascode arrangement may include multiple cascode transistors, each having gate terminals coupled to nodes of a voltage divider that is coupled between a positive voltage supply and a reference voltage supply. Emitter-follower bipolar junction transistors (BJTs) may be configured to control voltages at the gate terminals of the primary switching transistor and the cascode transistors to accommodate changes in the output voltage at the output terminal.

Switch with cascode arrangement

A switching device may include an input terminal, an output terminal, a primary switching transistor coupled between the input terminal and the output terminal, logic circuitry configured to receive a control signal to selectively activate the switching device, a first cascode arrangement coupled between the logic circuitry and a first reference voltage supply, and a second cascode arrangement coupled between the input terminal and the primary switching transistor. The first cascode arrangement may include cascode transistors having gate terminals coupled to a first voltage divider coupled between the first reference voltage supply and a second reference voltage supply that is coupled to the logic circuitry. The second cascode arrangement may include a first cascode transistor coupled to a fixed voltage at the first voltage divider and second and third cascode transistors coupled to variable cascode bias voltages at a second voltage divider coupled to a variable voltage input.

Embodiments of a device and method are disclosed. In an embodiment, a current sensing circuit includes first and second integrated resistors on a semiconductor die, a controllable current source configured to provide a reference current, and a current determination circuit. A resistance value of the second integrated resistor is a factor n larger than a resistance value of the first integrated resistor. A current drawn by a target circuit is configured to flow through the first integrated resistor, and the reference current is configured to flow through the second integrated resistor. The current determination circuit is configured to determine a value of the current drawn by the target circuit based on the value of the reference current when a first voltage at a terminal of the first integrated resistor is approximately equal to a second voltage at a terminal of the second integrated resistor.

Systems and methods for sensing a current in a circuit

Aspects of the subject disclosure may include, for example, obtaining, by a first circuit of a charge pump circuit, charge sourced from a power supply operative at a first voltage level, wherein the first circuit comprises a first plurality of transistors, and wherein each of the first plurality of transistors is rated for operation at an applied voltage that is less than the first voltage level, storing the charge in a first capacitor of the first circuit at a first point in time, and transferring the charge stored in the first capacitor to a second capacitor of a second circuit of the charge pump circuit at a second point in time such that the second capacitor stores the charge, wherein the second point in time is subsequent to the first point in time. Other embodiments are disclosed.

High-voltage charge pump using low-voltage technology

Embodiments of a device and method are disclosed. In an embodiment, a calibration circuit for a temperature sensor circuit includes a current source configured to generate a temperature independent reference current and further includes a voltage window generator circuit. The voltage window generator circuit is configured to generate a voltage window for the temperature sensor circuit using at least the temperature independent reference current. The voltage window is defined by a first reference voltage and a second reference voltage. The voltage window generator circuit is further configured to control a width of the voltage window to include a range of proportional to absolute temperature (PTAT) voltage outputs of a temperature sensor in the temperature sensor circuit.

Systems and methods for calibrating temperature sensors

Embodiments of a method and a device are disclosed. In an embodiment, a method for operating a bias controller for an amplifier circuit involves obtaining temperature data corresponding to a temperature of the amplifier circuit, generating a proportional to absolute temperature (PTAT) bias voltage based on a first PTAT slope when the temperature is within a first range of temperatures or a second PTAT slope when the temperature is within a second range of temperatures, wherein the second PTAT slope is greater than the first PTAT slope, and biasing the amplifier circuit based on the generated PTAT bias voltage.

Systems and methods for operating a bias controller for an amplifier circuit

Embodiments of systems and method for automatically biasing power amplifiers using a controllable current source are disclosed. In an embodiment, a bias controller for a power amplifier includes a first reference device source/drain interface, a first controllable current source configured to generate a first reference current in response to a first current control signal and to provide the first reference current to the first reference device source/drain interface, a first reference device gate interface, a first current-to-voltage controller configured to generate a first stabilized voltage in response to the first reference current and to provide the first stabilized voltage to the first reference device gate interface, and a first power amplifier (PA) interface configured to output a first control voltage in response to the first stabilized voltage.

Growing community of inventors

Chandler, AZ, United States of America

Xu Jason Ma