Globalfoundries Inc.

Globalfoundries U.S. Inc.

Xinyuan Dou

Hong Yu

Sipeng Gu

Zhenyu Hu

Yanzhen Wang

Xing Zhang

Xusheng Kevin Wu

Sunil Kumar Singh

Ravi Prakash Srivastava

Zhiguo Sun

Hongliang Shen

Akshey Sehgal

Guoliang Zhu

Hui Zang

Haiting Wang

Scott Beasor

Chun Yu Wong

Baofu Zhu

Edmund Kenneth Banghart

Sukwon Hong

Sandeep Gaan

Tao Han

Yongjun Shi

Hui Zhan

Ashish Kumar Jha

Jeffrey Chee

Shimpei Yamaguchi

Dongil Choi

Wenhe Lin

Md Khaled Hassan

Xiaobo Chen

Satyajit Shinde

Carlos Chacon

A semiconductor device is provided, which includes providing an active region, a source region, a drain region, a dielectric layer, a gate structure and a nitrogen-infused dielectric layer. The source region and the drain region are formed in the active region. The dielectric layer is disposed over the source region and the drain region. The gate structure formed in the dielectric layer is positioned between the source region and the drain region. The nitrogen-infused dielectric layer is disposed over the dielectric layer and over the gate structure.

Gate capping layers of semiconductor devices

A structure, an STI structure and a related method are disclosed. The structure may include an active region extending from a substrate; a gate extending over the active region; and a source/drain region in the active region, and an STI structure. The STI structure includes a liner and a fill layer on the liner along the opposed longitudinal sides of a lower portion of the active region, and the fill layer along the opposed ends of the active region. The liner may include a tensile stress-inducing liner that imparts a transverse-to-length tensile stress in at least a lower portion of the active region but not lengthwise. The liner can be applied in an n-FET region and/or a p-FET region to improve performance.

STI structure with liner along lower portion of longitudinal sides of active region, and related FET and method

This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor structure including two source/drain regions; a metal gate positioned on the semiconductor structure adjacent to and between the source/drain regions; a metal cap with a different metal composition than the metal gate and having a thickness in the range of approximately 0.5 nanometer (nm) to approximately 5 nm positioned on the metal gate; a first dielectric cap layer positioned above the semiconductor structure; an inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the metal gate, wherein an upper surface of the ILD has a greater height above the semiconductor structure than an upper surface of the metal gate; a second dielectric cap layer positioned on the ILD and above the metal cap; and a contact on and in electrical contact with the metal cap.

Integrated circuit structure to reduce soft-fail incidence and method of forming same

The present disclosure generally relates to semiconductor structures and, more particularly, to smooth sidewall structures and methods of manufacture. The method includes: forming a plurality of mandrel structures; forming a first spacer material on each of the plurality of mandrel structures; forming a second spacer material over the first spacer material; and removing the first spacer material and the plurality of mandrel structures to form a sidewall structure having a sidewall smoothness greater than the plurality of mandrel structures.

Method of forming smooth sidewall structures using spacer materials

Methods of reducing the SC GH on a FinFET device while protecting the LC devices and the resulting devices are provided. Embodiments include forming an ILD over a substrate of a FinFET device, the ILD having a SC region and a LC region; forming a SC gate and a LC gate within the SC and LC regions, respectively, an upper surface of the SC and LC gates being substantially coplanar with an upper surface of the ILD; forming a lithography stack over the LC region; recessing the SC gate; stripping the lithography stack; forming a SiN cap layer over the SC and LC regions; forming a TEOS layer over the SiN cap layer; and planarizing the TEOS layer.

Method to reduce FinFET short channel gate height

A shallow trench isolation (STI) structure is formed from a conventional STI trench structure of a first dielectric material extending into the substrate. The conventional STI structure undergoes further processing: removing a first portion of the dielectric material and adjacent portions of the semiconductor substrate to create a first recess, and then removing another portion of the dielectric material to create a second recess in just the dielectric material. A nitride spacer layer is formed above the remaining dielectric material and on the sidewalls of the substrate. A second dielectric material is formed on the spacer layer and fills the remainder of first and second recesses to a lever above the substrate. A nitride capping layer and another dielectric layer are disposed above the second material, thereby substantially encasing the STI structure in nitride. This provides a taller STI structure that results in a better fin profile during a subsequent fin reveal process.

Method to form high performance fin profile for 12LP and above

The present disclosure relates to semiconductor structures and, more particularly, to selective shallow trench isolation (STI) fill material for stress engineering in semiconductor structures and methods of manufacture. The structure includes a single diffusion break (SDB) region having at least one shallow trench isolation (STI) region with a stress fill material within a recess of the at least one STI region. The stress fill material imparts a stress on a gate structure adjacent to the at least one STI region.

Selective shallow trench isolation (STI) fill for stress engineering in semiconductor structures

Disclosed are a method of forming an integrated circuit (IC) structure with robust metal plugs and the resulting IC structure. In the method, openings are formed in an interlayer dielectric layer to expose semiconductor device surfaces. The openings are lined with a two-layer liner, which includes conformal metal and barrier layers, and subsequently filled with a metal layer. However, instead of waiting until after the liner is formed to perform a silicidation anneal, as is conventionally done, the silicidation anneal is performed between deposition of the two liner layers. This is particularly useful because, as determined by the inventors, performing the silicidation anneal prior to depositing the conformal barrier layer prevents the formation of microcracks in the conformal barrier layer. Prevention of such microcracks, in turn, prevents any metal from the metal layer from protruding into the area between the two liner layers and/or completely through the liner.

Middle of the line (MOL) contact formation method and structure

At least one method, apparatus and system is disclosed herein for forming a fin field effect transistor (finFET) device having a reduced breakdown voltage. The method comprises forming a first gate structure on a substrate of a semiconductor wafer in a first layer, the gate structure extending to a height of about h above the substrate. A trench is formed in the first layer adjacent the first gate structure and extends from a height of about d to the substrate. A connector is formed in the trench between the substrate and a layer of the finFET above the first layer. The process of forming the connector comprises; forming a thin film oxide on the sidewalls of the trench extending from a height below h to about d; forming a liner in the trench, extending over the substrate and on the sidewalls to about the height d over the thin film oxide and forming a layer of tungsten in the trench over the liner.

Methods, apparatus, and system for fabricating finFET devices with increased breakdown voltage

The disclosure relates to forming single diffusion break (SDB) and end isolation regions in an integrated circuit (IC) structure, and resulting structures. An IC structure according to the disclosure includes: a plurality of fins positioned on a substrate; a plurality of gate structures each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on and extending transversely across the plurality of fins between a pair of the plurality of gate structures; at least one single diffusion break (SDB) region positioned within the insulator region and one of the plurality of fins, the at least one SDB extending from an upper surface of the substrate to an upper surface of the insulator region; and an end isolation region positioned laterally adjacent to a lateral end of one of the plurality of gate structures.

Integrated circuit structure including single diffusion break and end isolation region, and methods of forming same

The present disclosure relates to semiconductor structures and, more particularly, to semiconductor structures with uniform gate heights and methods of manufacture. The structure includes: short channel devices in a first area of an integrated circuit die; and long channel devices in a second area of the integrated circuit die. The long channel devices have a same gate height as the short channel devices.

Semiconductor structure with uniform gate heights

One illustrative method disclosed herein includes, among other things, forming first and second fins for a short channel FinFET device ('SCD') and a long channel FinFET device ('LCD'), performing an oxidation process to form a sacrificial oxide material selectively on the channel portion of one of the first and second fins but not on the channel portion of the other of the first and second fins, removing the sacrificial oxide material from the fin on which it is formed so as to produce a reduced-size channel portion on that fin that is less than the initial size of the channel portion of the other non-oxidized fin, and forming first and second gate structures for the SCD and LCD devices.

Methods of forming short channel and long channel finFET devices so as to adjust threshold voltages

Disclosed is a method of forming a semiconductor structure that includes one or more fin-type field effect transistors (FINFETs) and single-diffusion break (SDB) type isolation regions that are within a semiconductor fin and that define the active device region(s) for the FINFET(s). The isolation regions are formed so that they include a semiconductor liner. The semiconductor liner ensures that, when a source/drain recess is formed immediately adjacent to the isolation region, the bottom and opposing sides of the source/drain recess will have semiconductor surfaces onto which epitaxial semiconductor material for a source/drain region is grown. As a result, the angle of the top surface of the source/drain region relative to the top surface of the semiconductor fin is minimized. Thus, the risk that a subsequently formed source/drain contact will not reach the source/drain region is also minimized. Also disclosed is a semiconductor structure formed according to the method.

Fin-type field effect transistors with single-diffusion breaks and method

Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an isolation trench between two fin structures on an integrated circuit substrate, forming a flowable film in the isolation trench using a flowable chemical vapor deposition process, and annealing the flowable film to form a silicon oxide dielectric layer in the isolation trench. The annealing is performed at a temperature of less than about 200&#xb0; C. with a process gas including Nand HO.

Growing community of inventors

Clifton Park, NY, United States of America

Xinyuan Dou