Chinese Academy of Sciences

Zing Semiconductor Corporation

Shanghai Simgui Technology Co., Ltd.

Xing Wei

Zhongying Xue

Xi Wang

Meng Chen

Minghao Li

Yongwei Chang

Guoxing Chen

Yun Liu

Miao Zhang

Lu Fei

Nan Gao

Chenglu Lin

Jing Lan Chen

Hao Wang

Fei Ye

Xun Wang

Tao Wei

Xiaolu Huang

Xiang Wang

Hongtao Xu

Xinhong Cheng

Yuehui Yu

Gongbai Cao

Zhan Li

Zhongdang Wang

Xin Su

The present invention provides a method for determining the type of defects in a monocrystalline silicon wafer, which includes the steps of: using LST to measure particles in an as-grown silicon wafer and thereby obtaining a first measurement, and determining a V-rich region based on the first measurement and a first preset density value; and subjecting the silicon wafer to a thermal treatment, again using LST to measure particles in the silicon wafer and thereby obtaining a second measurement, and determining a Pv region, an I-rich region and a Pi region based on the second measurement, a second preset density value and a third preset density value. As a result, a particle density can be utilized as a basis for accurately and efficiently determining a region of interest of a monocrystalline silicon wafer as one of a V-rich region, a Pv region, a Pi region and an I-rich region.

Method for determining types of defects in monocrystalline silicon wafer

The present application provides a method for verification of conductivity type of a silicon wafer. The method comprises measuring the resistivity of the silicon wafer to obtain a first resistivity, placing the silicon wafer under atmosphere of air for a predicted time period, measuring the resistivity of the silicon wafer to obtain a second resistivity, and determining conductivity type of the silicon wafer by comparing the first resistivity and the second resistivity. The method can be applied to a silicon wafer having a high resistivity such as higher than 500 ohmto rapidly and accurately determine conductivity type of the silicon wafer. Advantages of the method of the present application include accurate test results, easy operation, simple device requirement, and reduced cost.

Method for verification of conductivity type of silicon wafer

The invention provides a method of detecting crystallographic defects, comprising: sampling wafer of an ingot in complying with a predetermined wafer sampling frequency; identifying crystallographic defects of the wafer to show the crystallographic defects of the wafer; characterizing observation of the crystallographic defects of the wafer and extracting a value characterizing the crystallographic defects; through a result of characterizing the crystallographic defects, obtaining a radial distribution of density of the wafer and categorizing the crystallographic defects; and obtaining an isogram of the crystallographic defects of the wafer to show a crystallographic defect distribution of the whole ingot according to the value characterizing the crystallographic defects and categories of the crystallographic defects. It is no need to break the ingot to obtain the crystallographic defect distribution of the whole ingot, through which the technology for growing the ingot may be effectively adjusted to obtain the ingot with required characteristics of defect.

Method of detecting crystallographic defects and method of growing an ingot

The invention provides a measuring method of resistivity of a wafer, comprising: choosing a wafer to be measured, conducting a thermal treatment for the wafer to remove a thermal doner in the wafer, conducting an oxidation process for the wafer to form an oxidized surface on the wafer, and measuring resistivity of the wafer. In the method, firstly, the wafer is oxidized to get the oxidized surface, so as to restrict surface variation when placing the wafer in a later process. Therefore, the resistivity measurement of the wafer surface only slightly varies.

Measuring method of resistivity of a wafer

The present application provides a method for characterizing defects in silicon crystal comprising the following steps: etching a surface of the silicon crystal to remove a predicted thickness of the silicon crystal; conducting a LLS scanning to a surface of the etched silicon crystal to obtain a LLS map of the surface, a LSE size of defects, and defect bulk density; based on at least one of the LLS map of the surface, the LSE size of defects and the defect bulk density, determining a type of defect existing in the silicon crystal and/or a defect zone of each type of defect on the surface. By applying the method, the characterizing period and the characterizing cost can be reduced, plural defects such as vacancy, oxygen precipitate and dislocation can be characterized simultaneously, the characterizing accuracy can be enhanced, and the defect type and the defect zone can be determined with high reliability. In addition, the method can be applied to all crystal defect types, is easy to operate, and is an environmentally friendly method for determination of grown-in defects.

Method for characterizing defects in silicon crystal

A method of making a silicon on insulator structure comprises: providing a bonded structure, the bonded structure comprises the first substrate, the second substrate and the insulating buried layer, the insulating buried layer is positioned between the first substrate and the second substrate; peeling off a layer of removing region of the first substrate from the bonded structure to obtain a first film; at a first temperature, performing a first etching to etch the first film to remove a first thickness of the first film; at a second temperature, performing a second etching to etch the first film to planarize the first film and remove a second thickness of the first film, the first temperature being lower than the second temperature, the first thickness being greater than the second thickness, and a sum of the first thickness and the second thickness being a total etching thickness of the first film.

Silicon on insulator structure and method of making the same

The present disclosure provides a bonding method for a semiconductor substrate, which may improve flatness of a bonded substrate. The present disclosure further provides a bonded semiconductor substrate. The semiconductor substrate is thermally treated prior to bonding, and oxygen precipitates in the semiconductor substrate are partially or totally converted to interstitial oxygen atoms in the thermal treatment.

Bonding method for semiconductor substrate, and bonded semiconductor substrate

The present invention provides a method of making a silicon on insulator (SOI) structure, comprising steps of: providing a bonded structure, the bonded structure comprises a first substrate, a second substrate and an insulating buried layer, the insulating buried layer is positioned between the first substrate and the second substrate; peeling off a layer of removing region of the first substrate from the bonded structure to obtain a SOI structure; and processing the SOI structure with isothermal annealing technology at a pressure which is lower than atmospheric pressure.

Disclosed a heat shield structure for a single crystal production furnace, which is provided above a melt crucible of a single crystal production furnace and comprises an outer housing and a heat insulation plate disposed within the outer housing. A bottom outer surface of the outer housing faces an interior of the melt crucible, and an angle formed between a plane in which the heat insulation plate is located and a plane in which a bottom of the outer housing is located is an acute angle and faces an outer surface of single crystal silicon. The heat shield design is changed, a heat absorbing plate is additionally provided for transferring heat absorbed to the single crystal silicon, a heat channel is formed in the heat shield, so that a pulling rate is controlled, which improves radial mass uniformity of the single crystal silicon.

Heat shield structure for single crystal production furnace and single crystal production furnace

The present disclosure provides a method for cleaning a bonding interface before bonding. The method includes: providing a first surface and a second surface for bonding, the first surface being a non-crystal surface and the second surface being a crystal surface; and cleaning the first surface and the second surface with ammonia respectively before bonding, wherein at least one of parameters of an ammonia concentration and a cleaning temperature for cleaning the first surface is higher than a counterpart of parameters for cleaning the second surface.

Method for cleaning bonding interface before bonding

The present disclosure provides an annealing method for improving interface bonding strength of a wafer. The method includes: providing a substrate, the substrate having a bonding interface; performing a first annealing step, wherein the first annealing step is practiced in an oxygen-containing atmosphere, and an oxidation protection layer is formed on a surface of the substrate through the annealing step; and performing a second annealing step upon the first annealing step, wherein a temperature of the second annealing step is higher than that of the first annealing step, and the second annealing step is practiced in a nitrogen-free environment.

Annealing method for improving bonding strength

A method for preparing a substrate with an insulating buried layer includes: providing a substrate, the substrate having a supporting layer and an insulating layer arranged on a surface of the supporting layer; performing first ion implantation, implanting modified ions into the substrate, wherein a distance from an interface between the insulating layer and the supporting layer to a Gaussian distribution peak of modified ion concentration is less than 50 nm, such that the modified ions form a nano cluster in the insulating layer; and performing a second ion implantation, continuing to implant the modified ions into the insulating layer, wherein the ions are implanted in the same way as the first ion implantation, and a distance from a Gaussian distribution peak of modified ion concentration in this step to the Gaussian distribution peak of modified ion concentration in the first ion implantation is less than 80 nm.

Method for preparing substrate with insulated buried layer

The present disclosure provides a method for preparing a substrate with a carrier trapping center. The method includes: implanting bubbling ions into the semiconductor substrate to form a splitting layer, and implanting modified ions into the insulating layer to form a nano cluster; providing a supporting substrate; bonding the supporting substrate to the semiconductor substrate by using the insulating layer as an intermediate layer; performing a first heat treatment for the bonded substrate such that a splitting layer is formed at the position where the bubbling ions are implanted, and causing the semiconductor substrate to split at the position of the splitting layer; performing rapid thermal annealing for the substrate; and performing a second heat treatment for the rapidly thermally annealed semiconductor substrate to consolidate the bonding interface and form the nano cluster at the position where the modified ions are implanted.

Method for preparing substrate with carrier trapping center

A method for preparing a semiconductor substrate with an buried insulating layer by a guttering process, includes the following steps: providing a device substrate and a supporting substrate; forming an insulating layer on a surface of the device substrate; performing a heating treatment on the device substrate, so as to form a denuded zone on the surface of the device substrate; bonding the device substrate having the insulating layer with the supporting substrate, such that the insulating layer is sandwiched between the device substrate and the supporting substrate; annealing and reinforcing a bonding interface, such that an adherence level of the bonding interface meets requirements in the following chamfering grinding, thinning and polishing processes; performing the chamfering grinding, thinning and polishing processes on the device substrate which is bonded.

Method for preparing semiconductor substrate with insulating buried layer gettering process

A method for forming an edge-chamfered substrate with a buried insulating layer is provided, which comprises the following steps: providing a first substrate (S); forming an etching mask layer on surfaces of the first substrate, wherein said etching mask layer is formed on the whole surfaces of the first substrate (S); chamfering a glazed surface of the first substrate and the etching mask layer thereon by the edge grinding (S); by rotary etching, etching the first substrate which is exposed by the edge grinding on the etching mask layer (S); providing a second substrate (S); and bonding the first substrate to the second substrate with a buried insulating layer (S). The method avoids the edge collapses and the changes of the warp degree in subsequent processes.

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Shanghai, China

Xing Wei