Japan Science and Technology Agency

Kyushu Institute of Technology

System Jd Co., Ltd.

Xiaqing Wen

Seiji Kajihara

Kohei Miyase

Hiroshi Date

Yoshihiro Minamoto

Provided are a conversion device and the like for converting a initial test pattern given in advance into a test pattern of a bit constitution of different logic values, without losing the fault coverage of transition delay fault which can be detected by the constitution element of the initial test pattern. The conversion device converts an initial test patterngiven in advance for a logic circuit into an intermediate test patternof a bit constitution of different logic values, where the constitution elements of the initial test patternare at least two test vectors applied in succession. The conversion device includes a decision means for deciding a combination of logic values in the initial test patternwhich meet a detection condition of faults of the logic circuit which can be detected by applying the constitution elements.

Growing community of inventors

Fukuoka, Japan

Xiaqing Wen