Changxin Memory Technologies, Inc.

Xiaoyu Yang

Gongyi Wu

Yachao Xu

Liang Zhao

A method for forming a memory includes: forming a bit line structure and a capacitor contact layer, where the bit line structure includes a bit line, a bit line cap layer and a bit line isolation layer, and the capacitor contact layer covers part of a side wall of the bit line isolation layer; forming a stop layer covering the side wall of the bit line isolation layer; forming a capacitor landing layer covering a top surface of the capacitor contact layer; and etching the bit line isolation layer by using the stop layer as an etch stop layer to form an air gap in the bit line isolation layer. Probability of occurrence of a short circuit between the capacitor landing layer and a bit line is reduced.

Memory and method for forming same

The present disclosure provides a method for manufacturing capacitor array, including: forming, on an upper surface of the substrate, a laminated structure including sacrificial layers and support layers; forming a patterned mask layer on an upper surface of the laminated structure; etching the laminated structure based on the patterned mask layer to form a through hole, wherein after the through hole is formed, the patterned mask layer is retained on the upper surface of the laminated structure, and the through hole penetrates through the patterned mask layer and the laminated structure; forming a first electrode on a sidewall and at a bottom of the through hole; forming, in the patterned mask layer and the laminated structure, and removing the sacrificial layer based on the opening; forming a capacitor dielectric layer on a surface of the first electrode; and forming a second electrode on a surface of the capacitor dielectric layer.

Growing community of inventors

Hefei, China

Xiaoyu Yang