Freescale Semiconductor,inc.

Nxp Usa, Inc.

Freescale Semiconductors Inc.

Xiaowei Ren

Wayne R Burger

Robert A Pryor

Michele Lynn Miera

Robert Paul Davidson

Colin Kerr

Mark A Bennett

Paul W Sanders

Thuy B Dao

Michael F Petras

Daniel J Lamey

Joel E Keys

Jeffrey Kevin Jones

Margaret A Szymanowski

David Cobb Burdeaux

Mark A DeTar

Hernan A Rueda

Rodney Arlan Barksdale

An active semiconductor device, such as a laterally diffused metal oxide semiconductor (LDMOS) transistor, includes a substrate having a substrate resistivity of at least 1 kohm-cm. An active area of the active semiconductor device is formed in the substrate. A doped implant region is formed in the substrate surrounding the active area of the active semiconductor device and a field oxide region is formed over the doped implant region. The doped implant region may include a boron dopant. Methodology entails forming the doped implant region prior to formation of the field oxide region.

Active semiconductor device on high-resistivity substrate and method therefor

Embodiments of laterally diffused metal oxide semiconductor (LDMOS) transistors are provided. An LDMOS transistor includes a substrate having a source region, channel region, and a drain region. A first implant is formed to a first depth in the substrate. A gate electrode is formed over the channel region in the substrate between the source region and the drain region. A second implant is formed in the source region of the substrate; the second implant is laterally diffused under the gate electrode a predetermined distance. A third implant is formed to a second depth in the drain region of the substrate; the second depth is less than the first depth.

Laterally diffused metal oxide semiconductor transistors for radio frequency power amplifiers

Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., &#x2267;100 Ohm-cm) semiconductor substrates and lower resistance inductors for the IC. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. The active transistor(s) are formed in the substrate proximate the front face. Planar capacitors are also formed over the front face of the substrate. Various terminals of the transistor(s), capacitor(s) and inductor(s) are coupled to a ground plane on the rear face of the substrate using through-substrate-vias to minimize parasitic resistance. Parasitic resistance associated with the planar inductors and heavy current carrying conductors is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC previously unobtainable.

Monolithic microwave integrated circuits

Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., &#x2267;100 Ohm-cm) semiconductor substrates and lower resistance inductors for the IC. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. The active transistor(s) are formed in the substrate proximate the front face. Planar capacitors are also formed over the front face () of the substrate. Various terminals of the transistor(s), capacitor(s) and inductor(s) are coupled to a ground plane on the rear face of the substrate using through-substrate-vias to minimize parasitic resistance. Parasitic resistance associated with the planar inductors and heavy current carrying conductors is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC previously unobtainable.

Methods of making a monolithic microwave integrated circuit

A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and having a first conductivity type, a gate structure supported by the semiconductor substrate between the source and drain regions, a first well region in the semiconductor substrate, having a second conductivity type, and in which a channel region is formed under the gate structure during operation, and a second well region adjacent the first well region, having the second conductivity type, and having a higher dopant concentration than the first well region, to establish a path to carry charge carriers of the second conductivity type away from a parasitic bipolar transistor involving a junction between the channel region and the source region.

LDMOS minority carrier shunting

Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., &#x2267;100 Ohm-cm) semiconductor substrates () and lower resistance inductors (') for the IC (). This eliminates significant in-substrate electromagnetic coupling losses from planar inductors () and interconnections (--&#x2033;) overlying the substrate (). The active transistor(s) (&#x2032;) are formed in the substrate () proximate the front face (). Planar capacitors (&#x2032;) are also formed over the front face () of the substrate (). Various terminals (------&#x2032;, etc.) of the transistor(s) (&#x2032;), capacitor(s) (&#x2032;) and inductor(s) (&#x2032;) are coupled to a ground plane () on the rear face () of the substrate () using through-substrate-vias (&#x2032;) to minimize parasitic resistance. Parasitic resistance associated with the planar inductors (&#x2032;) and heavy current carrying conductors (-&#x2032;) is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC () previously unobtainable.

Monolithic microwave integrated circuit

Embodiments of integrated passive devices (e.g., metal insulator metal, or MIM, capacitors) and methods of their formation include depositing a composite electrode over a semiconductor substrate (e.g., on a dielectric layer above the substrate surface), and depositing an insulator layer over the composite electrode. The composite electrode includes an underlying electrode and an overlying electrode deposited on a top surface of the underlying electrode. The underlying electrode is formed from a first conductive material (e.g., AlCuW), and the overlying electrode is formed from a second, different conductive material (e.g., AlCu). The top surface of the underlying electrode may have a relatively rough surface morphology, and the top surface of the overlying electrode may have a relatively smooth surface morphology. For high frequency, high power applications, both the composite electrode and the insulator layer may be thicker than in some conventional integrated passive devices.

Integrated circuits including integrated passive devices and methods of manufacture thereof

A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and having a first conductivity type, a gate structure supported by the semiconductor substrate between the source and drain regions, a well region in the semiconductor substrate, having a second conductivity type, and in which a channel region is formed under the gate structure during operation, and a shunt region adjacent the well region in the semiconductor substrate and having the second conductivity type. The shunt region has a higher dopant concentration than the well region to establish a shunt path for charge carriers of the second conductivity type that electrically couples the well region to a potential of the source region.

LDMOS device with minority carrier shunt region

A lateral diffused metal oxide semiconductor (LDMOS) transistor is provided. The LDMOS transistor includes a substrate having a source region, channel region, and a drain region. A first implant is formed to a first depth in the substrate. A gate electrode is formed over the channel region in the substrate between the source region and the drain region. A second implant is formed in the source region of the substrate; the second implant is laterally diffused under the gate electrode a predetermined distance. A third implant is formed to a second depth in the drain region of the substrate; the second depth is less than the first depth. A method for forming the LDMOS transistor is also provided.

Methods of forming laterally diffused metal oxide semiconductor transistors for radio frequency power amplifiers

Electronic elements having an active device region and integrated passive device (IPD) region on a common substrate preferably include a composite dielectric region in the IPD region underlying the IPD to reduce electro-magnetic (E-M) coupling to the substrate. Mechanical stress created by plain dielectric regions and its deleterious affect on performance, manufacturing yield and occupied area may be avoided by providing electrically isolated inclusions in the composite dielectric region of a material having a thermal expansion coefficient (TEC) less than that of the dielectric material in the composite dielectric region. For silicon substrates, non-single crystal silicon is suitable for the inclusions and silicon oxide for the dielectric material. The inclusions preferably have a blade-like shape separated by and enclosed within the dielectric material.

Low loss substrate for integrated passive devices

Electronic elements having an active device region and bonding pad (BP) region on a common substrate desirably include a dielectric region underlying the BP to reduce the parasitic impedance of the BP and its interconnection as the electronic elements are scaled to higher power and/or operating frequency. Mechanical stress created by plain (e.g., oxide only) dielectric regions can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region having electrically isolated inclusions of a thermal expansion coefficient (TEC) less than that of the dielectric material in which they are embedded and/or closer to the substrate TEC. For silicon substrates, poly or amorphous silicon is suitable for the inclusions and silicon oxide for the dielectric material. The inclusions preferably have a blade-like shape separated by and enclosed within the dielectric material.

Electronic elements and devices with trench under bond pad feature

Electronic elements (&#x2033;) having an active device region () and integrated passive device (IPD) region () on a common substrate () preferably include a composite dielectric region (&#x2033;) in the IPD region underlying the IPD () to reduce electromagnetic (E-M) () coupling to the substrate (). Mechanical stress created by plain dielectric regions (') and its deleterious affect on performance, manufacturing yield and occupied area may be avoided by providing electrically isolated inclusions (&#x2033;) in the composite dielectric region (&#x2033;) of a material having a thermal expansion coefficient (TEC) less than that of the dielectric material (&#x2033;) in the composite dielectric region (&#x2033;). For silicon substrates (), non-single crystal silicon is suitable for the inclusions (&#x2033;) and silicon oxide for the dielectric material (&#x2033;). The inclusions (&#x2033;) preferably have a blade-like shape separated by and enclosed within the dielectric material (&#x2033;).

Electronic elements (&#x2033;) having an active device region () and bonding pad (BP) region () on a common substrate () desirably include a dielectric region underlying the BP () to reduce the parasitic impedance of the BP () and its interconnection () as the electronic elements (&#x2033;) are scaled to higher power and/or operating frequency. Mechanical stress created by plain (e.g., oxide only) dielectric regions (') can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region (&#x2033;) having electrically isolated inclusions (&#x2032;) of a thermal expansion coefficient (TEC) less than that of the dielectric material (&#x2033;) in which they are embedded and/or closer to the substrate () TEC. For silicon substrates (), poly or amorphous silicon is suitable for the inclusions (&#x2033;) and silicon oxide for the dielectric material (&#x2033;). The inclusions (&#x2033;) preferably have a blade-like shape separated by and enclosed within the dielectric material (&#x2033;).

Methods for forming an RF device with trench under bond pad feature

An integrated MIS capacitor structure has a bottom electrode, a capacitor dielectric overlying the bottom electrode, and a plurality of capacitor top plates overlying the capacitor dielectric. In one form each capacitor top plate has a principal dimension and a lesser dimension, wherein individual capacitor top plates of the plurality are arranged proximate and adjacent to one another in an array along respective principal dimensions thereof. The bottom electrode is shared among the plurality of capacitor top plates. At least one of a plurality of conductive stripes is positioned on opposite sides of each capacitor top plate along the principal dimension of a respective capacitor top plate. The structure also has a grounded top metal layer and an inter-level dielectric. An external ground via is disposed adjacent at least one side edge of the plurality of capacitor top plates.

RF power transistor with large periphery metal-insulator-silicon shunt capacitor

An integrated shunt capacitor comprises a bottom plate (), a capacitor dielectric () overlying a portion of the bottom plate, a top plate () overlying the capacitor dielectric, a shield () overlying a portion of the top plate (); and a metallization feature () disposed about and isolated from at least two sides of the top plate (), the metallization feature () for coupling the bottom plate () to the shield (). In one embodiment, an RF power transistor has an impedance matching network including an integrated shunt capacitor as described herein.

Growing community of inventors

Phoenix, AZ, United States of America

Xiaowei Ren