Syntest Technologies, Inc.

Kyushu Institute of Technology

Japan Science and Technology Agency

System Jd Co., Ltd.

Lptex Corporation

Kyushu University

Xiaoqing Wen

Laung-Terng Wang

Hsin-Po Wang

Po-Ching Hsu

Seiji Kajihara

Shih-Chia Kao

Shyh-Horng Lin

Meng-Chyi Lin

Laung-Terng (l-t) Wang

Khader S Abdel-Hafez

Kohei Miyase

Fei-Sheng Hsu

Boryau (Jack) Sheu

Hao-Jan Chao

Hiroshi Date

Yoshihiro Minamoto

Augusli Kifli

Sen-Wei Tsai

Chi-Chan Hsu

Ming-Tung Chang

Ta-Chia Yeh

Shun-Miin (Sam) Wang

Shianling Wu

Zhigang Wang

Zhigang Jiang

Yuta Yamato

Laung-Terng (l T) Wang

Laung-Terng (l -t) Wang

Jaehee Lee

Hsin-P Wang

A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.

Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit

A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N&#x3e;1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.

Multiple-capture DFT method for detecting or locating crossing clock-domain faults during self-test or scan-test

Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test

A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).

Computer-aided design system to automate scan synthesis at register-transfer level

The provided are a don't-care-bit identification method and program for identifying don't-care-bits from the first and the second input vectors in an input-vector pair while keeping the sensitization status of paths, in a combinational circuit, sensitized by applying the first and the second input vectors in serial to input lines of combinational circuit. The method identifies an unspecified bit from the first and the second input vectors Vand Vcomposed of logic values 0 and 1, which are applied to the combinational portion in a sequential circuit or to an independent combinational circuit. The method includes an identification step for identifying an unspecified bit from the first and the second input vectors, while keeping sensitization status of a part of or all of the paths, sensitized by applying the first and the second input vectors.

Don't-care-bit identification method and don't-care-bit identification program

Logic value determination method and program for identifying unspecified bits and determining logic values shortly. The method enables to control the total number of logic value differences between corresponding input and output lines of combinational circuit. The method includes the first step for determining, when output has a logic value and input has an unspecified value, that the unspecified bit has the logic value of output, the second step for determining, when output has an unspecified value and input has a logic value, the logic value of the unspecified bit by justification, and the third step for calculating, when input and output both have unspecified values, probabilities of output to have 0 and 1, and determining the logic value of the unspecified bit based on the difference between the probabilities. The third step is repeated until the total number reaches a target value.

Target logic value determination method for unspecified bit in test vector for combinational circuit and non-transitory computer-readable medium

Provided are a generation device to reduce launch switching activity, yield loss risk, and power consumption of testing, even in the at-speed scan testing, even with a small number of don't-care (X) bits in input bits as in test compression, without any impact on test data volume, fault coverage, performance, and circuit design, by putting focus on internal lines in the circuit. The generation device includes a target internal line selection unit, a target internal line distinction unit, an identification unit that identifies a bit to be an unspecified bit and a bit to be a logic bit in the input bits, and an assignment unit that assigns a logic value 1 or a logic value 0 to unspecified bits in the input bits. The identification unit includes an unspecified bit identification unit and an input logic bit identification unit.

Generating device, generating method, and program

In a combinational portion, when there is one or more unspecified bits in pseudo external input lines and there is no unspecified bit in pseudo external output lines, an assigning operation is carried out. In the combinational portion, when there is one or more unspecified bits in the pseudo external output lines and there is no unspecified bit in the pseudo external input lines, first and second justifying operations are carried out, and a necessary logic value is determined for an unspecified bit of the test cube. In the combinational portion, when there are one more unspecified bits not only in the pseudo external input lines but also the pseudo external output lines, an assigning operation, a justifying operation or first and second assigning/justifying operations are performed upon a focused bit pair.

Test method and test program of semiconductor logic circuit device

A test pattern generation method for determining if a combinational portionis defective, by applying test patterns to a semiconductor integrated circuitand comparing responses to the test patterns with expected responses, the method including: a first step of generating test patterns having logic bits for detecting defects and unspecified bits; a second step of selecting critical pathsgenerated by the application of the test patterns; a third step of identifying critical gates on the critical paths; and a fourth step of determining unspecified bits so that a critical capture transition metric, which indicates the number of the critical gates whose states are changed, is reduced; wherein by reducing the critical capture transition metric, output delays from the critical pathsare prevented, and thereby false testing can be avoided.

Test pattern generation method for avoiding false testing in two-pattern testing for semiconductor integrated circuit

Provided are a generation device and the like for generating a test vector which can reduce capture power efficiently. The generation devicegenerates a test vector for a logic circuit by assigning logic values to each of a plurality of unspecified bits (X-bits) included in a test cube. The generation deviceincludes a selection unitfor selecting, among the plurality of X-bits, a target X-bit, which is a target of assigning a logic value, a capture transition metric calculation unitfor calculating capture transition metric caused by a test cube including an X-bit, and a logic value assignment unitfor assigning, to the selected target X-bit, a logic value which causes the smaller capture transition metric, by applying the capture transition metric calculation means to a first test cube obtained by assigning a logic value 0 to the selected target X-bit and to a second test cube obtained by assigning a logic value 1 to the selected target X-bit, and by comparing a capture transition metric caused by a first test cube and a capture transition metric caused by a second test cube.

Generating device, generating method, program and recording medium

Provided are a conversion device and others for converting a test vector set so as to reduce a logic value difference generated before and after scan capture in outputs of scan cells included in a full scan sequential circuit. A conversion device converts a test vector set corresponding to the full scan sequential circuit. The conversion device comprises a setting unit for setting a candidate bit which can be a don't care bit and a fixed bit which cannot be the don't care bit according to predetermined constraint conditions based on an input-output relationship in the logic circuit in order to identify the don't care bit identifiable as don't care from each test vector of the test vector set, and a logic value deciding unit for deciding a logic value for the don't care bit in view of a relationship in a plurality of bit pairs in relation to a test cube including the don't care bit identified by the setting unit.

Conversion device, conversion method, program, and recording medium

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Sunnyvale, CA, United States of America

Xiaoqing Wen