Altera Corporation

Intel Corporation

Xiaohong Jiang

Hong Shi

Yuanlin Xie

Sujit Sharan

Kemal Aygun

Kyung Suk Oh

Hui Liu

Jianyong Xie

Arghya Sain

Jianmin Zhang

Lijiang Wang

Jianming Huang

Nathaniel Wright Unger

Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a first trace embedded in a package substrate. In an embodiment, the first trace comprises a first region, where the first region has a first width, and a second region, where the second region has a second width that is smaller than the first width.

Package design scheme for enabling high-speed low-loss signaling and mitigation of manufacturing risk and cost

In one embodiment, an integrated circuit die includes first and second inductor structures, a first ground conductor, a second ground conductor and a conductive trace. The first ground conductor provides a first ground pathway for the first inductor structure. The second ground conductor provides a second ground pathway for the second inductor structure. The conductive trace coupled between the first and second ground conductors may magnetically decouple the first and second inductor structures. In addition, the integrated circuit die may also include conductive guard ring structures that surround the first and second inductor structures. One of the conductive guard ring structures may be connected to the first grounding pathway and the other conductive guard ring structure may be connected to the second grounding pathway. The conductive guard ring structures may further magnetically decouple the first and second inductor structures.

Magnetically decoupled inductor structures

In one embodiment, an integrated circuit package includes a package substrate, a printed circuit board, an interposer structure and a transmission line bridge interconnect within the interposer. The interposer structure, which includes multiple interposer layers, may be formed on a top surface of the package substrate. The printed circuit board may be coupled to the package substrate through the transmission line bridge interconnect. The transmission line may be formed on at least one of the interposer layers. The transmission line may be utilized to convey signals between the package substrate and the printed circuit board. The transmission line may be a stripline transmission line or a micro-strip transmission line. The transmission line may have a low parasitic inductance and implementation of the transmission line does not introduce large dimensional discontinuity throughout that signal pathway. The integrated circuit package may be part of a circuit system that includes external circuits.

Tranmission line bridge interconnects

An integrated circuit package substrate may include a core layer and dielectric layers formed on top and bottom surfaces of the core layer. Routing traces such as stripline structures may be formed in some of the dielectric layers, whereas plated through hole (PTH) structures may be formed through the core layer. A first pair of PTHs that carry a first differential signal may be orthogonally intertwined with a second pair of PTHs that carry a second differential signal. Solder balls formed at the surface of the package substrate may include a first pair of solder balls that convey a first differential signal that is orthogonally intertwined with respect to a second pair of solder balls that convey a second differential signal. The package substrate may be mounted on a printed circuit board (PCB). Differential PCB vias could use the same BGA orthogonal pattern described above.

Integrated circuit package routing with reduced crosstalk

An integrated circuit (IC) package substrate with non-uniform dielectric layers is disclosed. The IC package substrate is a multilayer package substrate that has dielectric layers and metal layers stacked up alternately. The dielectric layers in the package substrate have different thickness. The metal layers may be ground, signal or power layers. A thicker dielectric layer is placed in between a signal layer and a power layer in the package substrate. The thicker dielectric layer may be at least twice as thick as other dielectric layers in the package substrate. The thicker dielectric layer may provide better impedance control in the package substrate.

IC package with non-uniform dielectric layer thickness

Integrated circuit packages with stripline structures are provided. An integrated circuit package substrate may include a core layer having top and bottom surfaces and dielectric layers formed on the top and bottom surfaces of the core layer. Stripline structures may be formed in at least some of the dielectric layers. A stripline trace may include signal routing conductors sandwiched between top and bottom ground planes. In particular, a dielectric layer may be formed between the signal conductors and the bottom ground plane to support the signal conductors, whereas a localized air region may be formed over the signal routing conductors separating the signal conductors from the top ground plane. If desired, the region above the signal routing conductors between the top ground plane and the signal routing conductors may be filled using other types of material having low loss and/or a dielectric constant that is frequency independent.

Multilayer integrated circuit packages with localized air structures

An integrated circuit package having a package substrate, an integrated circuit, and at least one solder ball is provided. The package substrate has first and second surfaces. The integrated circuit may be mounted on the first surface of the package substrate. The solder ball may be coupled to the second surface of the package substrate. The package substrate may include a substrate layer. The substrate layer may include a ground plane with an opening. The opening may be formed just above the solder ball. In one instance, the diameter of the opening is greater than the diameter of the solder ball pad.

Integrated circuit package with reduced pad capacitance

In one embodiment, a printed circuit board (PCB) comprises one or more signal contact pads on a surface of the PCB and a plurality of ground planes embedded in the PCB with at least the ground plane closest to the signal contact pads) having gaps in line with the trace(s). In another embodiment, a PCB comprises one or more signal traces on a first surface of the PCB, a plurality of ground planes embedded in the PCB, and at least one blind via interconnecting the ground planes. In still another embodiment, a PCB comprises one or more signal contact pads on a first surface of the PCB, a plurality of ground planes embedded in the PCB with at least the ground plane closest to the signal contact pad(s) having a gap in line with the signal contact pad(s), and at least one blind via interconnecting the ground planes. In still another embodiment, signal contact pads may be formed on both major surfaces of the PCB.

High performance PCB

An integrated circuit with an on-die compensation network is presented. The compensation network includes a compensation inductor that has one terminal coupled to a bump pad of the die. Another terminal of the inductor is connected to a metal layer underneath the compensation inductor, forming a pi-configuration with the bump pad. The metal layer routes input and output signals from the integrated circuit. The invention can be used in either flip chip or wire bond applications.

Compensation network using an on-die compensation inductor

Broadly speaking, the embodiments of the present invention fill the need for methods of designing vertical transmission lines for optimal signal transition in multi-layer BGA packages. By controlling the impedance and geometry continuity of micro vias in each micro via layer in the package to follow smooth impedance and geometry curves from layer to layer, the return loss and insertion loss of the transmission line can be reduced or controlled to within acceptable ranges.

Vertically tapered transmission line for optimal signal transition in high-speed multi-layer ball grid array packages

In one embodiment, signaling and ground contacts are located in at least two parallel, rectilinear rows along at least one edge of an interconnect package such as a BGA package. In one row, each of a plurality of ground contacts is located between two pairs of contacts for receiving differential signals. In the second row, each of a plurality of ground contacts is located between two pairs of contacts for transmitting differential signals and the ground contacts in the second row are offset by one column from the ground contacts in the first row. As a result, the ratio of signaling pairs to ground contacts is 2:2. Additional pairs of rows may also be used. In other embodiments, signaling and ground contacts are located in three parallel, rectilinear rows along at least one edge of the package.

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San Jose, CA, United States of America

Xiaohong Jiang