International Business Machines Corporation

Globalfoundries Inc.

Samsung Electronics Co., Ltd.

Other

Chartered Semiconductor Manufacturing Ltd (corporation)

Elpis Technologies Inc.

Xiao Hu Liu

Thomas M Shaw

Gareth Geoffrey Hougham

Baozhen Li

Griselda Bonilla

Michael Wayne Lane

Chih-Chao Yang

Dennis Merton Newns

Bruce Gordon Elmegreen

Dureseti Chidambarrao

Christopher Vincent Jahnes

Paul Alfred Lauro

Conal Eugene Murray

Glenn John Martyna

Chung H Lam

Mukta G Farooq

Son Van Nguyen

Vincent James McGahay

Gerard McVicker

Huan Hu

Lawrence Alfred Clevenger

Ning Li

Cyril Cabral, Jr

Stephen McConnell Gates

Katsuyuki Sakuma

Bruce Bennett Doris

Jeffrey P Gambino

Zhong-Xiang He

Kirk David Peterson

Arvind Kumar

Chandrasekharan Kothandaraman

Bucknell Chapman Webb

Frank Robert Libsch

Stephen Mark Rossnagel

Jon Alfred Casey

Robert L Wisnieff

Edward Crandal Cooney, Iii

Sung Kwon Kang

Geoffrey W Burr

Devendra K Sadana

Huilong Zhu

Stephen W Bedell

Keith E Fogel

Haining S Yang

Michael S Gordon

Alfred Grill

Sampath Purushothaman

Timothy Harrison Daubenspeck

Kenneth Parker Rodbell

Paul Michael Solomon

Matthew Earl Colburn

Sanjay C Mehta

Ronald G Filippi

Fuad Elias Doany

Christos Dimitrios Dimitrakopoulos

Ahmet Serkan Ozcan

Satyanarayana Venkata Nitta

Tom C Lee

Fen Chen

David L Questad

Vijayeshwar Das Khanna

Kuan-Neng Chen

Robert Hannon

Qiang Huang

Brian Richard Sundlof

Mark C H Lamorey

Theodorus E Standaert

Daniel C Edelstein

Ping-Chuan Wang

Haizhou Yin

Paul Stephen Andry

Jian Jim Wang

Elbert Emin Huang

Edmund Juris Sprogis

Andrew Herbert Simon

Jae Hun Kim

Hosadurga K Shobha

Joshua M Rubin

Meikei Ieong

Qiqing Christine Ouyang

Deborah A Neumayer

Dario Leonardo Goldfarb

George Frederick Walker

Junjing Bao

Kafai Lai

David Brian Stone

Erdem Kaltalioglu

Raschid Jose Bezama

Naftali Eliahu Lustig

Thomas L McDevitt

Steven Lorenz Wright

William Joseph Murphy

Xinwen Zhang

Thomas Anthony Wassick

Cornelia K Tsang

Jianshi Tang

Howard Smith Landis

Wiren Dale Becker

Raymond R Horton

Hormazdyar M Dalal

Embodiments and examples are disclosed for intelligent vehicle diagnostics using driving behavior modeling and monitoring. For one example, a data processing system for a vehicle includes a plurality of sensors and a vehicle control unit (VCU). The VCU may sample the output from each of the plurality of sensors and assemble a dataset which may be transmitted to a cloud computing center. The cloud computing center may apply statistical machine learning algorithms to the dataset and training data to develop a model of a user's expected driving behavior. The cloud computing center may transmit the model to the vehicle, wherein the VCU may utilize the model to monitor the user's driving behavior. In response to detecting driving behavior that is anomalous to the expected driving behavior, the VCU may diagnose the cause of the anomalous behavior and take one or more preventative actions based on the diagnosis.

Detecting and diagnosing anomalous driving behavior using driving behavior models

A method of fabricating ultra-thin chips is provided. The method includes patterning circuit elements onto a substrate such that sections of the substrate are exposed and etching trenches into the sections of the substrate to define pedestals respectively associated with a corresponding circuit element. The method further includes depositing stressor layer material onto the circuit elements and applying handling tape to the stressor layer material. In addition, the method includes at least one of weakening the substrate in a plane defined by base corners of the pedestals and initiating substrate cracking at the base corners of the pedestals to encourage spalling of the pedestals off the substrate.

Forming ultra-thin chips for flexible electronics applications

A semiconductor structure and a process for forming a semiconductor structure. There is a back end of the line wiring layer which includes a wiring line, a multilayer cap layer and an ILD layer. A metal-filled via extends through the ILD layer and partially through the cap layer to make contact with the wiring line. There is a reliability enhancement material formed in one of the layers of the cap layer. The reliability enhancement material surrounds the metal-filled via only in the cap layer to make a bottom of the metal-filled via that contacts the wiring line be under compressive stress, wherein the compressive reliability enhancement material has different physical properties than the cap layer.

Enhancement of iso-via reliability

A multi-chip package structure includes a package substrate, an interconnect bridge device, first and second integrated circuit chips, and a connection structure. The first integrated circuit chip is flip-chip attached to at least the interconnect bridge device. The second integrated circuit chip is flip-chip attached to the interconnect bridge device and to the package substrate. The interconnect bridge device includes (i) wiring that is configured to provide chip-to-chip connections between the first and second integrated circuit chips and (ii) an embedded power distribution network that is configured to distribute at least one of a positive power supply voltage and a negative power supply voltage to at least one of the first and second integrated circuit chips attached to the interconnect bridge device. The connection structure (e.g., wire bond, injection molded solder, etc.) connects the embedded power distribution network to a power supply voltage contact of the package substrate.

Multi-chip package structure having high density chip interconnect bridge with embedded power distribution network

Aspects include a method of manufacturing a flexible electronic structure that includes a metal or doped silicon substrate. Aspects include depositing an insulating layer on a silicon substrate. Aspects also include patterning a metal on a silicon substrate. Aspects also include selectively masking the structure to expose the metal and a portion of the silicon substrate. Aspects also include depositing a conductive layer including a conductive metal on the structure. Aspects also include plating the conductive material on the structure. Aspects also include spalling the structure.

Flexible electronics for wearable healthcare sensors

A piezoelectronic device with novel force amplification includes a first electrode; a piezoelectric layer disposed on the first electrode; a second electrode disposed on the piezoelectric layer; an insulator disposed on the second electrode; a piezoresistive layer disposed on the insulator; a third electrode disposed on the insulator; a fourth electrode disposed on the insulator; a semi-rigid housing surrounding the layers and the electrodes; wherein the semi-rigid housing is in contact with the first, third, and fourth electrodes and the piezoresistive layer; wherein the semi-rigid housing includes a void. The third and fourth electrodes are on the same plane and separated from each other in the transverse direction by a distance.

Piezoelectronic device with novel force amplification

A method for constructing an advanced crack stop structure is described. An interconnection structure is formed comprised of a plurality of levels. Each level has an interconnect structure section and a crack stop section. In a first level of the interconnection structure, a high modulus layer is formed in the crack stop recess but not the interconnect recess and a barrier layer and a conductive metal layer is formed in both the interconnection recess and the crack stop recess of the first level. In a second level of the interconnection structure and the crack stop structure, a second high modulus layer is formed in the crack stop recess but not the interconnect recess and a barrier layer and a conductive metal layer is formed in both the interconnection recess and the crack stop recess of the second level. The barrier layers and high modulus layers are deposited in different steps.

Advanced crack stop structure

An integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a first plurality of levels. Each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The structure also includes a crack stop area which includes a crack stop structure having a second plurality of levels. The interconnect and crack stop structures have an equal number of levels. A third plurality of the crack stop structure levels include a high modulus layer unique to the respective crack stop structure level as compared to the corresponding interconnect structure level.

A method for creating an integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a plurality of levels, each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The IC structure also includes a crack stop area which includes a crack stop structure having an equal plurality of levels as the interconnect structure. Each of the crack stop structure levels includes at least one of the layers of the interconnection structure at a same level. At least one crack stop structure level also includes a high modulus layer unique to the crack stop structure level as compared to the corresponding interconnect structure level. In another aspect of the invention, a method for producing the structure is described.

An integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a plurality of levels, each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The IC structure also includes a crack stop area which includes a crack stop structure having an equal plurality of levels as the interconnect structure. Each of the crack stop structure levels includes at least one of the layers of the interconnection structure at a same level. At least one crack stop structure level also includes a high modulus layer unique to the crack stop structure level as compared to the corresponding interconnect structure level.

A combined nanofluidic and integrated circuit device includes a semiconductor wafer, which includes a substrate with active circuitry formed in the substrate; an oxide layer deposited adjacent the active circuitry; a stressor film deposited onto or into the oxide layer in sections, wherein the stressor film has a higher coefficient of thermal expansion than the oxide layer has; and a nanochannel formed in the oxide layer between the sections of the stressor film. According to an exemplary embodiment, the nanochannel is formed in the oxide layer by cooling the oxide layer and the stressor film to a fracture propagation temperature that is less than first and second temperatures at which the oxide layer and the stressor film are deposited on the substrate.

Nanofluidic channel fabrication by controlled spontaneous fracturing

A method is provided to supply power to wafer-scale ICs. The method includes receiving a wafer containing ICs placed on the top of the wafer. The wafer has through-silicon vias to provide power from the bottom to the ICs. The method also includes a printed circuit board, which has power rails in a pattern on the top of the printed circuit board, where the rails provide voltage and ground. The method continues with placing metal solder spheres between the bottom of the wafer and the top of the printed circuit board, where the spheres provide connections between the two, and where the spheres are free to move and operate as mechanical springs to resist clamping forces. The method also includes applying clamping pressure to the structure to establish connections by compressing the spheres, where no soldering is required.

Wafer-scale power delivery

An integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a first plurality of levels. Each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The structure also includes a crack stop area which includes a crack stop structure having a second plurality of levels. The interconnect and crack stop structures have an equal number of levels. A third plurality of the crack stop structure levels include a high modulus layer unique to the respective crack stop structure level as compared to the corresponding interconnect structure level. In another aspect of the invention, a method for fabricating the structure is described.

An integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a plurality of levels, each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The IC structure also includes a crack stop area which includes a crack stop structure having an equal plurality of levels as the interconnect structure. Each of the crack stop structure levels includes at least one of the layers of the interconnection structure at a same level. At least one crack stop structure level also includes a high modulus layer unique to the crack stop structure level as compared to the corresponding interconnect structure level. In another aspect of the invention, a method for producing the structure is described.

A semiconductor structure and a process for forming a semiconductor structure. There is a back end of the line wiring layer which includes a wiring line, a cap layer and an ILD layer. A metal-filled via extends through the ILD layer to make contact with the wiring line. There is a reliability enhancement material in the cap layer. The reliability enhancement material surrounds the metal-filled via only in the cap layer to make a bottom of the metal-filled via that contacts the wiring line be under compressive stress, wherein the compressive reliability enhancement material has different physical properties than the cap layer. The reliability enhancement material may be compressive as deposited or may be made compressive after deposition.

Growing community of inventors

Briarcliff Manor, NY, United States of America

Xiao Hu Liu