Zte Corporation

Zhuhai Access Semiconductor Co., Ltd

Xi'an Zhongxing New Software Co., Ltd.

Xianming Chen

Bo Dai

Kun Liu

Huiying Fang

Weiwei Yang

Benxia Huang

Lei Feng

Shuqiang Xia

Jing Shi

Wen Zhang

Yejie Hong

Wenshi Wang

Zhaohua Lu

Jindong Feng

Bingsen Xie

Jianxun Ai

Lina Jiang

Minxiong Li

Min Gu

Jiangjiang Zhao

Gao Huang

Wei Luo

Huahua Xiao

Xianghui Han

Wei Cao

Zhisong Zuo

Wei Bin Lin

Zhifeng Yuan

Xincai Li

Yifei Yuan

Dengkui Zhu

Qian Dai

Shupeng Li

Jian Peng

Yanfeng Guan

Chunlin Yan

Weiyuan Yang

Jida Zhang

Jun Gao

Xiaowei Xu

Shigui Xin

Disclosed are a method for manufacturing a support frame structure and a support frame structure. The support frame structure is used for embedded packaging, and includes: a metal plate comprising a support region and an opening region, at least one upper dielectric hole and at least one lower dielectric hole being formed respectively in upper and lower surfaces of the support region, the upper dielectric hole being communicated with the lower dielectric hole; at least one set of metal pillars comprising an upper metal pillar and a lower metal pillar, the upper metal pillar and the lower metal pillar being vertically connected to upper and lower surfaces of the metal plate, respectively; a dielectric layer comprising an upper dielectric layer and a lower dielectric layer, the upper dielectric layer and the lower dielectric layer being correspondingly formed on the upper surface of the metal plate and the upper dielectric hole and on a lower surface of the metal plate and the lower dielectric hole, respectively; and at least one core embedding cavity arranged in the opening region, running through the dielectric layer and the metal plate, and spaced from the upper dielectric hole and the lower dielectric hole by the dielectric layer.

Support frame structure and manufacturing method thereof

A manufacturing method for a conductive substrate with a filtering function includes preparing a core layer and forming first and second conductive holes in the core layer, forming a sacrificial copper layer on the first conductive hole and on the core layer, forming a metal layer on the second conductive hole, forming a metal post in the first conductive hole, forming a lower insulating layer on the core layer, forming a lower insulative post in the second conductive hole, forming a magnet wrapping around the metal post to obtain a first conductive post, forming an upper insulating layer on the core layer, forming an upper insulative post in the second conductive hole to obtain a second conductive post, removing the upper insulating layer, the lower insulating layer, and the remaining sacrificial copper post layer, followed by flattening.

Conductive substrate and carrier plate wiring structure with filtering function, and manufacturing method of same

A hybrid embedded packaging structure and a manufacturing method thereof are disclosed. The structure includes: a substrate with a first insulating layer, a conductive copper column, a chip-embedded cavity and a first circuit layer; a first electronic device arranged inside the chip-embedded cavity; a second electronic device arranged on a back surface of the first electronic device; a second insulating layer covering and filling the chip-embedded cavity and an upper layer of the substrate, exposing part of the first circuit layer and a back surface of part of the second electronic device or part of the first electronic device; a second circuit layer electrically connected with the conductive copper column and a terminal of the first electronic device; a conducting wire electrically connecting the first circuit layer with a terminal of the second electronic device; and a protection cover arranged on the top surface of the substrate.

Hybrid embedded packaging structure and manufacturing method thereof

Provided are a data transmission method and apparatus, and a storage medium. The method includes: receiving second downlink control information over a second search space, and rejecting receiving first downlink control information over a first search space; wherein the second downlink control information comprises downlink control information for carrying feedback of a base station.

Data transmission method and apparatus, and storage medium

A multi-device graded embedding package substrate includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer includes a first conductive copper pillar layer and a first device cavity. The second dielectric layer includes a first wiring layer located in a lower surface of the second dielectric layer, a second conductive copper pillar layer and a heat dissipation copper block layer provided on the first wiring layer. The third dielectric layer includes a second wiring layer, a third conductive copper pillar layer provided on the second wiring layer. A first device is attached to the bottom of the first device cavity, and a terminal of the first device is in conductive connection with the second wiring layer. A second device is attached to the bottom of a second device cavity penetrating through the first, second and third dielectric layers.

Multi-device graded embedding package substrate and manufacturing method thereof

A system and method for allocating network resources are disclosed herein. In one embodiment, the system and method are configured to perform: receiving a resource allocation message indicative of a plurality of resource groups allocated for a signal; and transmitting the signal using a portion of the plurality of resource groups, wherein, in a frequency domain, the portion of the plurality of resource groups presents a hopping pattern comprising at least a first hopping path that is associated with a first plurality of increasing frequency spacings and a second hopping path that is associated with a second plurality of decreasing frequency spacings.

System and method for transmitting a signal

Disclosed is an embedded chip package, comprising at least one chip and a frame surrounding the at least one chip, the chip having a terminal face and a back face separated by a height of the chip, the frame having a height equal to or larger than the height of the chip, wherein the gap between the chip and the frame is fully filled with a photosensitive polymer dielectric, the terminal face of the chip being coplanar with the frame, a first wiring layer being formed on the terminal face of the chip and a second wiring layer being formed on the back face of the chip. Moreover, a method for manufacturing an embedded chip package is disclosed.

Embedded chip package and manufacturing method thereof

Disclosed are a heat dissipation-electromagnetic shielding embedded packaging structure, a manufacturing method thereof, and a substrate. The heat dissipation-electromagnetic shielding embedded packaging structure includes: a dielectric layer including an upper surface and a lower surface, wherein at least one hollow cavity unit is disposed inside the dielectric layer; an insulating layer disposed in the hollow cavity unit, wherein the hollow cavity unit is partially filled with the insulating layer; an electronic element, wherein one end is embedded in the insulating layer, the other end is exposed in the hollow cavity unit, and the electronic element includes terminals; a through hole penetrating through the upper surface and the lower surface of the dielectric layer and communicating with the terminals; and a metal layer covering the six surfaces of the dielectric layer and the interior of the through hole to form a shielding layer and circuit layer respectively.

Heat dissipation-electromagnetic shielding embedded packaging structure, manufacturing method thereof, and substrate

In a method of manufacturing a connector, a first copper pillar layer and a sacrificial copper pillar layer are formed on a temporary bearing plate coated with copper, an etch stop layer is applied on the sacrificial copper pillar layer and electroplated to form a second copper pillar layer, insulating materials is laminated to form a first dielectric layer, a first circuit layer is formed on the first dielectric layer, a second copper pillar layer and a sacrificial copper pillar layer are extended on the first circuit layer, and a sacrificial copper layer is formed on the first circuit layer, insulating material is laminated on the first circuit layer to form a second dielectric layer, the temporary bearing plate is removed, a second and third circuit layers are simultaneously formed on the first and second dielectric layers, and the sacrificial copper layer and the sacrificial copper pillar layer are etched.

Connector for implementing multi-faceted interconnection

A method for manufacturing an embedded package structure having an air resonant cavity according to an embodiment includes manufacturing a first substrate including a first insulating layer, a chip embedded in the insulating layer, and a wiring layer on a terminal face of the chip of the first substrate, wherein the wiring layer is provided thereon with an opening revealing the terminal face of the chip; manufacturing a second substrate which comprises a second insulating layer; locally applying a first adhesive layer on the wiring layer such that the opening revealing the terminal face of the chip is not covered; and applying a second adhesive layer on the second substrate; and attaching and curing the first adhesive layer of the first substrate and the second adhesive layer of the second substrate to obtain an embedded package structure having an air resonant cavity on the terminal face of the chip.

Method for manufacturing embedded package structure having air resonant cavity

A circuit prearranged heat dissipation embedded packaging structure according to an embodiment of the present disclosure includes at least one chip and a support frame surrounding the at least one chip. The support frame may include a via pillar passing through the support frame in the height direction, a first wiring layer on a first surface of the support frame, and a heat dissipation layer on the back face of the chip. The first wiring layer is flush with or higher than the first surface, the first wiring layer is in conductive connection with the heat dissipation layer, a gap between the chip and the frame is completely filled with the dielectric material, a second wiring layer is formed on a terminal face of the chip, and the second wiring layer is in conductive connection with the first wiring layer through the via pillar.

Circuit prearranged heat dissipation embedded packaging structure and manufacturing method thereof

A packaging structure with an antenna and a manufacturing method thereof are disclosed. The packaging structure includes a package, an antenna circuit, an interconnecting circuit, an outer-layer circuit, and a chip. The package is internally packaged with a first conducting through hole column and a second conducting through hole column. The antenna circuit is disposed on a first surface and a sidewall of the package. The interconnecting circuit is packaged in the package, and is connected to the antenna circuit by the first conducting through hole column. The outer-layer circuit is disposed on a second surface of the package, and is connected to the interconnecting circuit by the second conducting through hole column. The outer-layer circuit is further connected to a conductive pin. The chip is packaged in the package, and is connected to the interconnecting circuit or the outer-layer circuit.

Packaging structure with antenna and manufacturing method thereof

Disclosed is a substrate manufacturing method for realizing three-dimensional packaging, which includes: preparing a base plate, the base plate including a dielectric material layer, a first sidewall pad, a first through-hole pillar and a cavity, the cavity being filled with a first metal block; processing a first circuit layer and a second circuit layer, the first circuit layer including a first padding plate and a second metal block, and the second circuit layer including a second padding plate and a plurality of pin pads; processing and laminating interlayer through-hole pillars; processing a third circuit layer and a fourth circuit layer, the third circuit layer including a second sidewall pad and the fourth circuit layer including a routing circuit; and etching to expose the first sidewall pad, the second sidewall pad and the pin pads.

Substrate manufacturing method for realizing three-dimensional packaging

Disclosed is a manufacturing method for an embedded structure. The method includes: preparing a temporary carrier board; preparing a second circuit layer on at least one of the upper surface and the lower surface of the temporary carrier board, and preparing a first dielectric layer to cover the second circuit layer; patterning and curing the first dielectric layer to form a cavity, mounting a device in the cavity, and performing hot-curing, wherein a surface of the device provided with a terminal faces an opening of the cavity; and preparing a second dielectric layer, wherein the device is embedded in the second dielectric layer, and a surface of the second dielectric layer is higher than a surface of the terminal by a preset value.

Embedded structure, manufacturing method thereof and substrate

Disclosed are a signal transmitting method, device and system, and a storage medium. The method includes: transmitting a first signal, the first signal includes at least one of: at least one first structure or at least one second structure. Each first structure includes at least one symbol group, each symbol group in the each first structure includes a cyclic prefix and at least one symbol, or a cyclic prefix, at least one symbol and guard time, and symbols of each symbol group occupy a same subcarrier or a same frequency resource in frequency domain. Each second structure includes at least one symbol group, each symbol group includes a cyclic prefix and at least one symbol, or a cyclic prefix, at least one symbol and guard time, and symbols of each symbol group in the each second structure occupy a same subcarrier or a same frequency resource in frequency domain.

Growing community of inventors

Shenzhen, China

Xianming Chen