Intel Corporation

Xiang Yin Zeng

Jiangqi He

Daoqiang Lu

John J Tang

BaoShu Xu

Wei Shi

Hyunjun Kim

Qing A Zhou

Jiamiao Tang

Ping Sun

Ding Hai

Guizhen Zheng

Robert L Sankman

Mostafa Naguib Abdulla

Henry Xu

Jianmin Li

Ming Dong Cui

Gregory V Christensen

Daoqiang (Daniel) Lu

Jiamiao(John) Tang

Disclosed are embodiments of a multi-chip assembly including optically coupled die. The multi-chip assembly may include two opposing substrates, and a number of die are mounted on each of the substrates. At least one die on one of the substrates is in optical communication with at least one opposing die on the other substrate. Other embodiments are described and claimed.

Multi-chip assembly with optically coupled die

An article includes a top electrode that is embedded in a solder mask. An article includes a top electrode that is on a core structure. A process of forming the top electrode includes reducing the solder mask thickness and forming the top electrode on the reduced-thickness solder mask. A process of forming the top electrode includes forming the top electrode over a high-K dielectric that is in a patterned portion of the core structure.

Integrated capacitors in package-level structures, processes of making same, and systems containing same

An embodiment of the present invention is a technique to construct a multi-die package. A stack of dice is formed from a base substrate in a package. The dice are positioned one on top of another and have copper plated segments for die interconnection. The dice are interconnected using copper plating to connect the copper plated segments.

Copper plating connection for multi-die stack in substrate package

A spiral inductor is disposed above a substrate that includes two different materials. A dielectric film is the first material that provides structural integrity for the substrate. A second dielectric is the second material that provides a low dielectric-constant (low-K) material closest to the spiral inductor coil. A process of forming the spiral inductor includes patterning the substrate to allow a recess as a receptacle for the second dielectric, followed by forming the spiral inductor mostly above the second dielectric.

Packaged spiral inductor structures, processes of making same, and systems containing same

A process includes mating a first heat spreader and a second heat spreader, such that the first heat spreader at a mating surface and second heat spreader at a mating surface become parallel and adjacent. The process includes placing a first die in a first die recess of the first heat spreader, and placing a second die in a second die recess in the second heat spreader. The process includes reflowing thermal interface material between each die and respective heat spreader. Thereafter, the process includes separating the first heat spreader and the second heat spreader. A package is achieved by the process, with reduced thicknesses. The package can be disposed onto a mounting substrate. The package can be assembled into a computing system.

Dual heat spreader panel assembly method for bumpless die-attach packages, packages containing same, and systems containing same

In one embodiment, the present invention includes a semiconductor package with lossy material inserts. The lossy material inserts may reduce electronic noise such as package resonance. Other embodiments are described and claimed.

Substrate with lossy material insert

A package may include a substrate provided with noise absorbing material. The noise absorbing material may absorb noise from a signal path in the substrate to prevent the noise from reaching other signals or signal paths.

Package level noise isolation

A method includes mating a first heat spreader and a second heat spreader, such that the first heat spreader at a mating surface and second heat spreader at a mating surface become parallel and adjacent. The mated first heat spreader and second heat spreader have at least one convection channel disposed therebetween. A process includes placing a first die in a first die recess of the first heat spreader, and placing a second die on a second die site on the second heat spreader. The process includes reflowing thermal interface material between each die and respective heat spreader. A package is achieved by the method, with reduced thicknesses. The package can be coupled through a bumpless build-up layer. The package can be assembled into a computing system.

Dual-chip integrated heat spreader assembly, packages containing same, and systems containing same

An integrated circuit with reduced pad capacitance, having a trench formed in the silicon substrate below the pad to reduce the pad capacitance. In another embodiment, an encapsulated air cavity is formed underneath the pad.

Reducing input capacitance of high speed integrated circuits

A method to reduce parasitic mutual capacitances in embedded passives. A first capacitor is formed by first and second electrodes embedding a dielectric layer. A second capacitor is formed by third and fourth electrodes embedding the dielectric layer. The third and first electrodes are etched from a first metal layer. The fourth and second electrodes are etched from a second metal layer. The first and the fourth electrodes are connected by a connection through the dielectric layer to shield a mutual capacitance between the first and second capacitors.

Reducing parasitic mutual capacitances

Embodiments of the invention relate to the construction of a dual die package with a high-speed interconnect. A package is created having a first die on a first side of a base substrate and a second die on a second side of the base substrate in opposed relation to the first die. A first copper plated interconnect is plated to the base substrate. Second copper interconnects are formed to connect the first copper plated interconnect to the first and second dice, respectively, such that the first and second dice are interconnected.

Dual die package with high-speed interconnect

Electronic devices and methods for their formation are described. One device relates to an electronic assembly including a substrate having a first surface and a second surface opposite the first surface. The electronic assembly also includes at least one RF front-end module coupled to the first surface of the substrate, and a ground plane layer positioned on the second surface of the substrate. The electronic assembly also includes an insulating layer on the ground plane layer, with the ground plane layer positioned between the second surface and the insulating layer. In addition, the electronic assembly also includes an antenna layer on the insulating layer, with the insulating layer positioned between the antenna layer and the ground plane layer.

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Shanghai, China

Xiang Yin Zeng