Sandisk Technologies Inc.

Intel Corporation

Western Digital Technologies, Inc.

Xiang Yang

Deepanshu Dutta

Huai-Yuan Tseng

Jiacen Guo

Abhijith Prakash

Gerrit Jan Hemink

Dengtao Zhao

Ken Oowada

Jiahui Yuan

Muhammad Masuduzzaman

Jianzhi Wu

Yu-Chung Lien

Toru Miwa

Ohwon Kwon

Wei Cao

Shantanu R Rajwade

Yi Song

Xiaochen Zhu

Chin-Yi Chen

Shubhajit Mukherjee

Ali Khakifirooz

Yanli Zhang

Peng Zhang

Kou Tei

Takayuki Inoue

Yan Li

Masaaki Higashitani

James K Kai

Zhenming Zhou

Pranav Kalavade

Henry Chin

Mohan Dunga

Wei Zhao

Aaron Lee

Tai-Yuan Tseng

Hua-Ling Cynthia Hsu

Parth Amin

Lito De La Rama

Tarek Ahmed Ameen Beshari

Piyush Dak

Fanqi Wu

Johann Alsmeier

Peter Rabkin

Liang Li

Jun Wan

Zhongguang Xu

Yuki Mizutani

Guirong Liang

Brian Murphy

YenLung Li

Jin Liu

Ke Zhang

Koichi Matsuno

Sagar Upadhyay

Matthias Baenninger

Narayanan Ramanan

Hiroyuki Mizukoshi

Swaroop Kaza

Erika Penzo

Xiaojia Jia

Kazuki Isozumi

Matin Amani

Xiaochang Miao

Minna Li

Arka Ganguly

Arun Thathachary

Laidong Wang

Albert Chen

Linnan Chen

Weiyi Li

Chao Qin

Stanley Jeong

Kun-Huan Shih

A memory apparatus and method of operation are provided. The apparatus includes source-side and drain-side select gate transistors for coupling respectively to the source-side and drain-side of memory holes of memory cells. During the read operation, the control means ramps the word lines to a read pass voltage. The control means is configured to delay ramping the voltage applied to the source-side select gate transistors to a select gate voltage until a predetermined time after the selected ones of the word lines and the unselected ones of the word lines ramp to the read pass voltage. The control means is also configured to delay ramping the voltage applied to the drain-side select gate transistors to a select gate voltage until a different predetermined time after the selected ones of the word lines and the unselected ones of the word lines ramp to the read pass voltage.

Delayed select gate ramp-up for peak read current consumption reduction for non-volatile memory apparatus

The memory device includes a die with a plurality of memory blocks which are physically arranged in six planes. The die is configured to allow parallel operations in memory blocks of any combination of all six plane. The memory device also includes circuitry that is configured to operate the die in at least two different operating modes depending on a type of memory product that the die is connected with. The at least two operating modes include a four-plane operating mode, wherein memory blocks in only four of the six planes can be selected simultaneously, and a six-plane operating mode, wherein memory blocks in all six planes can be selected simultaneously.

Memory device with multiple plane functionalities

Technology is disclosed herein for a memory system that includes control circuits that are configured to connect to a three-dimensional memory structure. The memory structure includes NAND strings arranged in a plurality of rows, a plurality of bit lines connected to the NAND strings and a plurality of word lines, each word line coupled to the plurality of rows of NAND strings. The control circuits are configured to, in a program-verify operation, sense memory cells of a first row of NAND strings coupled to the selected word line for a first sense time and sense memory cells of a second row of NAND strings coupled to the selected word line for a second sense time while applying a program-verify voltage to the selected word line.

Memory program-verify with adaptive sense time based on row location

Technology is disclosed herein for detecting evolved bad blocks in three-dimensional NAND. The test may include a drain side erase that includes applying an erase voltage from the bit lines and a source side erase that includes applying an erase voltage from the source line(s). If the source side erase performed worse than the drain side erase this may indicate a defect near the source side of the block. For example, the source side erase may fail but the drain side erase may pass. As another example the source side erase may take at least a pre-determined number of additional erase pulses to pass than the drain side erase. If the block is found as having a defect the entire block could be marked bad or the defective region could be identified such that the defective region is no longer used.

Evolving bad block detection in non-volatile memory

The memory device includes a memory block with an array of memory cells that are arranged in word lines. The word lines are in electrical communication with respective word line drivers and switches. Control circuitry is configured to program the memory cells of a selected word line in a programming operation during which the control circuitry applies an elevated voltage to the selected word line and receives a command to suspend the programming operation. With the word line switch associated with the selected word line turned on, the control circuitry ramps the selected word line from the elevated voltage to a reduced gate holding voltage and then turn the word line switch associated with the selected word line off to electrically isolate the selected word line from the associated word line driver so that the selected word line remains at the gate holding voltage until the programming operation resumes.

Suspend-resume-go techniques for memory devices

The techniques include a memory device receiving a data write instruction. The memory device programs the memory cells of the memory blocks to a one bit per memory cell (SLC) format with a first and second SLC data states. In response to the data programmed to the memory cells of the memory blocks reaching an SLC limit prior to completion of the data write instruction, without erasing the memory cells, the memory device programs at least some of the memory cells from the SLC format to a two bits per memory cell (MLC) format. When programming from the SLC format to the MLC format, the memory device inhibits programming of some of the memory cells in the first and second SLC data states to form a first MLC data state and programs other memory cells of the SLC data states to form second, third, and fourth MLC data states.

In-place write techniques without erase in a memory device

Memory die management based on biasing voltages. Some memory dies are formed of memory holes having a semi-circular shape. This semi-circular shape results in a decrease in biasing voltage compared to memory holes having a circular shape. Systems and methods described herein organize memory dies into memory die groups according to their biasing voltages. During operation, data is relocated between the memory die groups based on how often the data is read. Data may be scrambled within their respective memory die groups to maintain appropriate storage space.

Memory die management

A memory device is provided and includes a memory block that has a plurality of memory cells that are arranged in a plurality of word lines. The memory device also includes a plurality of word line switch transistors that are electrically coupled with the plurality of word lines, where the plurality of word lines are grouped into a plurality of zones based on a size of a word line switch transistor associated with each word line of the plurality of word lines. The memory device also includes a bitline biasing circuit for providing a negative biasing voltage to a bitline corresponding to a memory cell of the selected word line during programming of the selected word line and the bitline biasing circuit is configured to set a magnitude of the negative biasing voltage based on which zone of the plurality of zones the selected word line is in.

Enabling significant scaling of wordline switch with wordline dependent negative bitline voltage

The memory device includes a memory block with an array of memory cells arranged word lines. The memory device also includes control circuitry that is configured to program final data into a selected word line in a multi-pass programming operation that includes a first pass and a second pass. In the first pass, the control circuitry is configured to program the memory cells of the selected word line to foggy data and program parity data in the memory device. The parity data includes three possible data states. Prior to the second pass, the control circuitry is configured to read the foggy data and the parity data and reconstruct the final data from the foggy data and the parity data. In the second pass, the control circuitry is configured to program the memory cells of the selected word line from the foggy data to the final data.

Multi-stage programming techniques with three states per memory cell parity

A method and system for executing a dynamic 1-tier scan on a memory array are provided. The memory array includes a plurality of memory cells organized into a plurality of sub-groups. The dynamic 1-tier scan includes executing an program loop in which cells of a first sub-group are counted to determine whether a numeric threshold is met, and, if the numeric threshold is met with respect to the first sub group, at least one additional program loop is executed in which cells of a second sub-group are counted to determine whether the numeric threshold is met with respect to the second sub-group.

Dynamic 1-tier scan for high performance 3D NAND

A memory device includes a memory block including a plurality of sub-blocks each including a plurality of memory cells and control circuitry configured to perform single-side erase operations on the memory block in a sub-block mode in which a selected sub-block of the plurality of sub-blocks in the memory block is erased while unselected sub-blocks of the plurality of sub-blocks in the memory block are not erased and selectively perform data scrubbing and relocation operations on the plurality of sub-blocks of the memory block. To perform a data scrubbing and relocation operation, the control circuitry is configured to determine whether to perform the data scrubbing and relocation operation on a first sub-block based on a position of the first sub-block relative to an erase side of the memory block and selectively perform the data scrubbing and relocation operation on the first sub-block in response to the determination.

Single block mode block handling for single-side GIDL erase

Technology for mixed lockout verify. In a first programming phase, prior to a pre-determined data state completing verification, a no-lockout program verify is performed. After the pre-determined data state has completed verification, a lockout program verify is performed. The no-lockout verify may include charging all bit lines associated with the group to a sensing voltage to perform. The lockout verify may include selectively charging to the sensing voltage only bit lines associated with memory cells in the group to be verified. Bit lines associated with memory cells in the group that are not to be verified may be grounded to perform the lockout verify.

Mixed bitline lockout for QLC/TLC die

A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes coupled to bit lines. A control means successively applies each of a series of pulses of a program voltage to selected ones of the word lines while simultaneously applying one of a bit line program voltage and a bit line inhibit voltage to ones of the bit lines coupled to the memory holes containing groups of the memory cells connected to the selected ones of the plurality of word lines to program the groups of the memory cells with data. The control means maintains a voltage applied to ones of the plurality of bit lines as the bit line inhibit voltage in response to the ones of the plurality of bit lines remaining unselected when programming a next one of the groups of the memory cells.

Active current consumption save mode for non-volatile memory using fast programming

The memory device includes a memory block with memory cells arranged in word lines that are divided into sub-blocks. Control circuitry is configured to program each of the word lines of a selected sub-blocks in a plurality of program loops. During at least one program loop, the control circuitry applies a programming pulse to a selected word line. The control circuitry is also configured to simultaneously apply a verify voltage to the selected word line and a pass voltage to unselected word lines. In a first phase of a multi-phase pre-charge process, the control circuitry reduces the voltages applied to the selected word line and at least one unprogrammed word line to a low voltage. In a second phase that follows the first phase, the control circuitry reduces the voltages applied to all word lines that remained at the pass voltage to the low voltage.

Channel pre-charge process in a memory device

The memory device includes at least one memory block with a plurality of memory cells arranged in a plurality of word lines. The memory device includes control circuitry that is configured to program the memory cells of the at least one memory block in a plurality of program loops. The control circuitry is further configured to receive a command to write user data to the memory device. On at least a portion of a selected word line of the plurality of word lines, the control circuitry is configured to perform a smart verify operation to acquire a smart verify programming voltage. After the smart verify programming voltage is acquired, in a plurality of program loops, the control circuitry is configured to program the memory cells of the selected word line to include the user data and data that corresponds to the smart verify programming voltage.

High performance verify techniques in a memory device

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Santa Clara, CA, United States of America

Xiang Yang