Sandisk Technologies Inc.

Intel Corporation

Western Digital Technologies, Inc.

Xiang Yang

Deepanshu Dutta

Huai-Yuan Tseng

Jiacen Guo

Abhijith Prakash

Gerrit Jan Hemink

Dengtao Zhao

Wei Cao

Jiahui Yuan

Ken Oowada

Muhammad Masuduzzaman

Peng Zhang

Jianzhi Wu

Yu-Chung Lien

Toru Miwa

Ohwon Kwon

Chin-Yi Chen

Shantanu R Rajwade

Yi Song

Xiaochen Zhu

Shubhajit Mukherjee

Ali Khakifirooz

Yanli Zhang

Kou Tei

Takayuki Inoue

Yan Li

Masaaki Higashitani

James K Kai

Zhenming Zhou

Pranav Kalavade

Henry Chin

Mohan Dunga

Aaron Lee

Wei Zhao

Tai-Yuan Tseng

Hua-Ling Cynthia Hsu

Parth Amin

Lito De La Rama

Tarek Ahmed Ameen Beshari

Piyush Dak

Fanqi Wu

Johann Alsmeier

Peter Rabkin

Liang Li

Jun Wan

Zhongguang Xu

Jonathan Huynh

Yuki Mizutani

Guirong Liang

Brian Murphy

YenLung Li

Jin Liu

Koichi Matsuno

Ke Zhang

Sagar Upadhyay

Matthias Baenninger

Narayanan Ramanan

Hiroyuki Mizukoshi

Swaroop Kaza

Erika Penzo

Kazuki Isozumi

Xiaojia Jia

Matin Amani

Xiaochang Miao

Minna Li

Arka Ganguly

Arun Thathachary

Albert Chen

Laidong Wang

Linnan Chen

Weiyi Li

Khanh Nguyen

Chao Qin

Stanley Jeong

Kun-Huan Shih

The memory device includes a quick pass write (QPW) voltage source and a transistor that can control the supply of a first QPW bias voltage to a plurality of bit lines. Control circuitry programs the memory cells of a selected word line in a plurality of program loops. For each memory cell in the selected word line, the control circuitry determines if the memory cell is within either a first or a second QPW zone. If the memory cell is in the second QPW zone, the control circuitry connects the QPW voltage source to the bit line that is in communication with that memory cell to supply the first QPW bias voltage to the bit line. In response to a determination that the memory cell is in the first QPW zone, the control circuitry controls the transistor to supply an average second QPW bias voltage to the bit line.

Generation of quick pass write biases in a memory device

The memory device includes a memory block that has a plurality of memory cells that are arranged in a plurality of word lines and in a plurality of channels. The memory device also includes circuitry that is configured to conduct a hole pre-charge operation to inject holes into the plurality of channels. During the hole pre-charge operation, the circuitry applies a positive CELSRC pre-charge voltage to a source line of the memory block and applies a negative unselected word line pre-charge voltage to a plurality of unselected word lines in the memory block to make a plurality of memory cells in the memory block conductive to holes.

Channel pre-charge process for memory devices using hole pre-charge operation

To improve programming performance in NAND memory, while maintaining programming accuracy and reducing program disturb, the channel pre-charge phase before a programming pulse can be eliminated. Instead, a read recovery phase after the program verify directly discharges a selected word line from the verify voltage to a negative word line voltage, with non-selected word lines being directly discharged from the read bypass voltage to the negative word line voltage. From the negative word line voltage, the word lines are then ramped up to ground and then on the bias levels of the following programming pulse. These conditions can drive electrons from the charge storage region of the selected memory cell, resulting in a high degree of channel boosting and much less program disturb. Variations of the technique can be applied to NAND memory operable in a sub-block mode where it can be difficult to use the typical channel pre-charge.

Negative word line enabled pre-boosting strategy to improve NAND program performance

A block of non-volatile memory cells is divided into a first sub-block and a second sub-block. Programming non-volatile memory cells of the second sub-block after programming non-volatile memory cells of the first sub-block comprises boosting unselected channels in the second sub-block to a boosted condition; prior to boosting unselected channels in the second sub-block to the boosted condition, boosting unselected channels in the first sub-block to the boosted condition to pre-charge the channels of the second sub-block; and applying a program voltage to a selected word line of the second sub-block while channels in the first sub-block are in the boosted condition and channels in the first sub-block are in the boosted condition.

Non-volatile memory with efficient precharge in sub-block mode

A storage device is disclosed herein. The storage device comprises a non-volatile memory, where the non-volatile memory includes a block of 3N wordlines partitioned into a plurality of sub-blocks. The plurality of sub-blocks include an upper sub-block of a first subset of the block of 3N wordlines, a lower sub-block of a second subset of the block of 3N wordlines, and a middle sub-block of a third subset of the block of 3N wordlines. Further, the storage device comprises control circuitry coupled to the block of 3N wordlines and configured to: perform a program operation in a normal order programming sequence on the upper sub-block; perform a program operation in a reverse order programming sequence on the lower sub-block; and perform a program operation in the reverse order programming sequence on the middle sub-block.

Multi-tier sub-block mode operation

A non-volatile memory includes a plurality of non-volatile memory cells arranged in blocks. Each block includes multiple sub-blocks that can be independently erased and programmed. A control circuit is connected to the non-volatile memory cells. The control circuit is configured to independently erase and program sub-blocks of a same block. The control circuit is configured to only allow one sub-block per block to be open at a time.

Non-volatile memory with sub-blocks

A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the word lines and the strings and is configured to successively apply one of a series of pulses of a program voltage to each selected one of the word lines to program the memory cells connected thereto during a program operation. The control means is also configured to utilize a time of a preliminary period of the program operation based on the one of the series of pulses of the program voltage being applied. The preliminary period of the program operation is before the series of pulses of the program voltage are applied to each selected one of the plurality of word lines.

Single-level cell pump skip program operation preliminary period timing optimization for non-volatile memory

The memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines. The plurality of word lines include a selected word line, a pair of neighboring word lines that are immediately adjacent the selected word line, and a plurality of non-neighboring word lines that are not immediately adjacent the selected word line. Circuitry can perform a sensing operation on at least one memory cell in the selected word line. During the sensing operation, the circuitry is configured to apply a reference voltage to the selected word line, apply different first and second pass voltages to the neighboring word lines, and apply a third pass voltage that is different than the first and second pass voltages to the plurality of non-neighboring word lines. The circuitry is further configured to sense a threshold voltage of the at least one memory cell.

Asymmetric VREADK to reduce neighboring word line interference in a memory device

While programming a first set of memory cells, a non-volatile memory apparatus determines an initial magnitude of a programming signal for a second set of memory cells based on testing during the programming of the first set of memory cells. The testing comprises sensing at a first test voltage level and sensing at a second test voltage level without apply a voltage spike between the two sensing operation. Removing the voltage spike results in a performance increase (i.e. faster programming speed) and as well as a decrease in power usage.

Non-volatile memory with efficient setting of initial program voltage

The memory device includes a memory block with memory cells that are arranged in word lines, some of which are reconfigurable word lines that are dummy word lines when the memory block is operating in a one bit per cell mode and are data word lines when the memory block is operating in a multiple bits per cell mode. Circuitry is configured to program the memory cells of a selected word line. The circuitry determines if the selected word line is a reconfigurable word line. If the selected word line is not a reconfigurable word line, the circuitry programs the memory cells of the selected word line with a first programming scheme. If the selected word line is a reconfigurable word line, the circuitry programs the memory cells of the selected word line with a second programming scheme that is different than the first programming scheme.

Reconfigurable lines in different sub-block modes in a NAND memory device

A memory apparatus and method of operation are provided. The apparatus includes source-side and drain-side select gate transistors for coupling respectively to the source-side and drain-side of memory holes of memory cells. During the read operation, the control means ramps the word lines to a read pass voltage. The control means is configured to delay ramping the voltage applied to the source-side select gate transistors to a select gate voltage until a predetermined time after the selected ones of the word lines and the unselected ones of the word lines ramp to the read pass voltage. The control means is also configured to delay ramping the voltage applied to the drain-side select gate transistors to a select gate voltage until a different predetermined time after the selected ones of the word lines and the unselected ones of the word lines ramp to the read pass voltage.

Delayed select gate ramp-up for peak read current consumption reduction for non-volatile memory apparatus

The memory device includes a die with a plurality of memory blocks which are physically arranged in six planes. The die is configured to allow parallel operations in memory blocks of any combination of all six plane. The memory device also includes circuitry that is configured to operate the die in at least two different operating modes depending on a type of memory product that the die is connected with. The at least two operating modes include a four-plane operating mode, wherein memory blocks in only four of the six planes can be selected simultaneously, and a six-plane operating mode, wherein memory blocks in all six planes can be selected simultaneously.

Memory device with multiple plane functionalities

Technology is disclosed herein for a memory system that includes control circuits that are configured to connect to a three-dimensional memory structure. The memory structure includes NAND strings arranged in a plurality of rows, a plurality of bit lines connected to the NAND strings and a plurality of word lines, each word line coupled to the plurality of rows of NAND strings. The control circuits are configured to, in a program-verify operation, sense memory cells of a first row of NAND strings coupled to the selected word line for a first sense time and sense memory cells of a second row of NAND strings coupled to the selected word line for a second sense time while applying a program-verify voltage to the selected word line.

Memory program-verify with adaptive sense time based on row location

Technology is disclosed herein for detecting evolved bad blocks in three-dimensional NAND. The test may include a drain side erase that includes applying an erase voltage from the bit lines and a source side erase that includes applying an erase voltage from the source line(s). If the source side erase performed worse than the drain side erase this may indicate a defect near the source side of the block. For example, the source side erase may fail but the drain side erase may pass. As another example the source side erase may take at least a pre-determined number of additional erase pulses to pass than the drain side erase. If the block is found as having a defect the entire block could be marked bad or the defective region could be identified such that the defective region is no longer used.

Evolving bad block detection in non-volatile memory

The memory device includes a memory block with an array of memory cells that are arranged in word lines. The word lines are in electrical communication with respective word line drivers and switches. Control circuitry is configured to program the memory cells of a selected word line in a programming operation during which the control circuitry applies an elevated voltage to the selected word line and receives a command to suspend the programming operation. With the word line switch associated with the selected word line turned on, the control circuitry ramps the selected word line from the elevated voltage to a reduced gate holding voltage and then turn the word line switch associated with the selected word line off to electrically isolate the selected word line from the associated word line driver so that the selected word line remains at the gate holding voltage until the programming operation resumes.

Suspend-resume-go techniques for memory devices

Growing community of inventors

Santa Clara, CA, United States of America

Xiang Yang