Semiconductor Manufacturing International (shanghai) Corporation

Infineon Technologies Ag

Other

International Business Machines Corporation

Semiconductor Manufacturing International (beijing) Corporation

Infineon Technologies North America Corp.

Xian Jay Ning

Hanming Wu

John Chen

Joachim Nuetzel

Keith Kwong Hon Wong

Jiang Zhang

Ravikumar Ramachandran

Rainer Leuschner

Michael C Gaidis

Kwong Hon Wong

Rajiv M Ranade

Gill Yong Lee

William C Wille

Jianhua Ju

Kia-Seng Low

Greg Costrini

George Stojakovic

Bei Zhu

Christian Arndt

Yi Sheng Hsieh

A method for manufacturing a semiconductor device having improved contact structure includes providing a semiconductor substrate, forming a plurality of gate structures formed on a portion of the substrate, forming an interlayer dielectric layer overlying the gate structures, and forming a first copper interconnect layer overlying the substantially flat surface region of the interlayer dielectric layer. The method further includes forming a dielectric layer overlying the first copper interconnect layer, forming a second copper interconnect layer overlying the dielectric layer, and providing a copper ring structure enclosing an entirety of an inner region of the dielectric layer, the copper ring structure being provided between the first copper interconnect layer and the second copper interconnect layer to maintain the inner region of the dielectric layer. In addition, the method includes forming a bonding pad structure overlying a region within the inner region of the dielectric layer.

Bond pad for low K dielectric materials and method for manufacture for semiconductor devices

The present invention provides a design method for circuit layout and a rapid thermal annealing method for a semiconductor apparatus. The design method includes: establishing a ternary relationship among a device electric parameter, an annealing temperature and a distributing density of STI patterns, and establishing a binary relationship between the device electric parameter and a gate pattern length; obtaining a difference between distributing densities of STI patterns in a particular region and in a target region; obtaining an electric parameter difference corresponding to the difference between the distributing densities of STI patterns according to the ternary relationship; obtaining a gate pattern length difference corresponding to the electric parameter difference according to the binary relationship; and adjusting a gate pattern length in the particular region according to the gate pattern length difference. As compared with a traditional design method, the design method for circuit layout provided by the invention does not need adding dummy structure patterns, thereby avoiding negative influence to normal electric performance of the semiconductor apparatus by adding dummy structures.

Method for circuit layout and rapid thermal annealing method for semiconductor apparatus

An integrated circuit device structure with a novel contact feature. The structure includes a substrate, a dielectric layer overlying the substrate, and a metal interconnect overlying the dielectric layer. A first interlayer dielectric layer is formed surrounding the metal interconnect. A second interlayer dielectric layer of a predetermined thickness is overlying the first interlayer dielectric layer. A trench opening of a first width is formed within an upper portion of the second interlayer dielectric layer. A first barrier layer is within and is overlying the trench opening of the first width. A contact opening of a second width is within a lower portion of the second interlayer dielectric layer. The second width is less than the first width. The lower portion of the second interlayer dielectric layer is coupled to the upper portion of the second interlayer dielectric layer within the predetermined thickness of the second interlayer dielectric. A second barrier layer is within and is overlying the opening of the contact opening and overlying the first barrier layer. A directional partially or completely removal of the second barrier forming a low contact resistance structure. A copper material is formed overlying the first barrier layer and the second barrier layer to substantially fill the contact opening and the trench within the second interlayer dielectric layer.

Method of forming a via structure dual damascene structure for the manufacture of semiconductor integrated circuit devices

A structure using pure silicon dioxide hard marsk for gate pattern. In an embodiment, the present invention provides a partially completed semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device has a gate structure including edges and a substantially pure silicon dioxide mask structure overlying the gate structure. A thickness ranging from about 400 to about 600 Angstroms of the substantially pure silicon dioxide mask structure is included. The device has a dielectric layer forming sidewall spacers on the edges of the gate structure to protect the gate structure including the edges and an exposed portion of the pure silicon dioxide mask structure overlying the gate structure. The device has an epitaxially grown fill material in an etched source region and an etched drain region.

Method and structure using a pure silicon dioxide hardmask for gate patterning for strained silicon MOS transistors

A semiconductor device having an improved contact structure. The device has a semiconductor substrate and a plurality of gate structures formed on the substrate. The device has a first interlayer dielectric overlying the gate structures. The device has a first copper interconnect layer overlying the first interlayer dielectric layer. The device also has a first low K dielectric layer overlying the first copper interconnect layer. A second copper interconnect layer is overlying the low K dielectric layer. In between the first and second copper layers is a copper ring structure enclosing an entirety of an inner region of the first low K dielectric layer. In a preferred embodiment, the copper ring structure is provided between the first copper interconnect layer and the second copper interconnect layer to maintain the inner region of the first low K dielectric layer. A bonding pad structure is overlying a region within the inner region.

A method for forming a CMOS integrated circuit using strained silicon technology. The method forms a liner layer overlying the first gate structure and the second gate structure and overlying first source/drain regions in the first well region and second source/drain regions in the second well region. In a preferred embodiment, the method patterns A spacer dielectric layer to form first sidewall spacer structures on the first gate structure, including the first edges and to form the second sidewall spacer structures on the second gate structure, including the second edges, while using a portion of the liner layer as a stop layer. The method maintains the liner layer overlying the first source/drain regions and second source/drain regions during at least the patterning of the spacer dielectric layer according to a preferred embodiment. The method also etches a first source region and a first drain region adjacent to the first gate structure using the hard mask layer and the first sidewall spacers as a protective layer. The method deposits a silicon germanium fill material into the first source region and the first drain region to fill the etched first source region and the etched first drain region while causing the first channel region between the first source region and the first drain region to be strained in compressive mode from at least the silicon germanium material formed in the first source region and the first drain region.

Single mask scheme method and structure for integrating PMOS and NMOS transistors using strained silicon

A semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device also has a gate structure including edges. A metal hard mask layer is overlying the gate structure. A dielectric layer is formed sidewall spacers on the edges of the gate structure to protect the gate structure including the edges. An exposed portion of the metal hard mask layer is overlying the gate structure. A silicon germanium fill material is provided in an etched source region and an etched drain region. The etched source region and the etched drain region are each coupled to the gate structure. The device has a strained channel region between the filled source region and the filled drain region from at least the silicon germanium material formed in the etched source region and the etched drain region. An electrical connection is coupled to the metal hard mask overlying the gate structure. Optionally, the device has a second metal layer overlying the metal hard mask.

Metal hard mask method and structure for strained silicon MOS transistors

Techniques for an integrated circuit device are provided. The integrated circuit device includes a substrate, an active circuit area, and a dielectric layer. A seal ring surrounds the active circuit area. At least one corner area of the integrated circuit includes a plurality of corner band stacks. Each of the plurality of corner band stacks is oriented at about a predetermined angle and extends from a first sawing trace to a second sawing trace. In a specific embodiment, if a structural fault in the at least one corner area occurs, the structural fault is predisposed to extend at about the predetermined angle.

Seal ring corner design

A method for fabricating a semiconductor device. The method includes providing a semiconductor substrate including a surface region. The method forms a first interlayer dielectric overlying the surface region and forms an interconnect layer overlying the first interlayer dielectric layer. The method also forms a low K dielectric layer overlying the interconnect layer, which has a predetermined shape. The method forms a copper interconnect layer overlying the low K dielectric layer. In a preferred embodiment, the low K dielectric layer maintains the predetermined shape using a dummy pattern structure provided within a portion of the low K dielectric layer to mechanically support and maintain the predetermined shape of the low K dielectric layer between the interconnect layer and the copper interconnect layer.

Dummy patterns and method of manufacture for mechanical strength of low K dielectric materials in copper interconnect structures for semiconductor devices

A method for forming a CMOS semiconductor wafer. The method includes providing a semiconductor substrate (e.g., silicon wafer) and forming a dielectric layer (e.g., silicon dioxide, silicon oxynitride) overlying the semiconductor substrate. The method includes forming a gate layer overlying the dielectric layer and patterning the gate layer to form a gate structure including edges. The method includes forming a dielectric layer overlying the gate structure to protect the gate structure including the edges. Preferably, the dielectric layer has a thickness of less than 40 nanometers. The method includes etching a source region and a drain region adjacent to the gate structure using the dielectric layer as a protective layer and depositing silicon germanium material into the source region and the drain region to fill the etched source region and the etched drain region. The method causes a channel region between the source region and the drain region to be strained in compressive mode from at least the silicon germanium material formed in the source region and the drain region. The method includes forming a second protective layer overlying surfaces and performing an anisotropic etching process to form spacer structures to seal the gate structure.

Method and structure for second spacer formation for strained silicon MOS transistors

A method for forming CMOS integrated circuits. The method forms a blanket layer of silicon dioxide overlying an entirety of the surface region of a first well region and a second well region provided on a semiconductor substrate. The blanket layer of silicon dioxide is overlying the hard mask on the first gate structure and the second gate structure. The blanket layer of silicon dioxide is also overlying a region to be protected. Depending upon the embodiment, the region can be a sidewall spacer structure and portion of an MOS device on a peripheral region of the substrate. Of course, there can be other variations, modifications, and alternatives. The method protects the region to be protected using a masking layer, while the surface region of the first well region and the second well region being exposed. The method selectively removes exposed portions of the blanket layer of silicon dioxide, including the hard mask on the first gate structure and the second gate structure, while exposing a first polysilicon material on the first gate structure and while exposing a second polysilicon material on the second gate structure. The method strips the masking layer. The method also includes forming a silicided layer overlying the first polysilicon material on the first gate structure and the second polysilicon material on the second gate structure, while the region to be protected remains free from the silicided layer.

Integration scheme method and structure for transistors using strained silicon

Techniques for an integrated circuit device are provided. The integrated circuit device includes a semiconductor substrate, an integrated circuit, a dielectric layer, and a sealing structure. The sealing structure surrounds the integrated circuit and is disposed within the dielectric layer to prevent damage to the integrated circuit. The sealing structure includes a plurality of metal traces organized in vertical layers and a plurality of vias. Each via of the plurality of vias couples at least two metal traces of the plurality of metal traces from adjacent vertical layers. Each via of the plurality of vias contacts at least two orthogonal surfaces of a lower metal trace of the at least two metal traces. The plurality of metal traces and plurality of vias form a continuous boundary.

Seal ring structures with unlanded via stacks

A partially completed semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device has a gate structure including edges and a substantially pure silicon dioxide mask structure overlying the gate structure. A thickness ranging from about 400 to about 600 Angstroms of the substantially pure silicon dioxide mask structure is included. The device has a dielectric layer forming sidewall spacers on the edges of the gate structure to protect the gate structure including the edges and an exposed portion of the pure silicon dioxide mask structure overlying the gate structure. The device has an epitaxially grown fill material (e.g., silicon/germanium, silicon carbide) in an etched source region and an etched drain region. Preferably, the etched source region and the etched drain region are coupled to the gate structure. The device has a strained channel region between the filled source region and the filled drain region from at least the fill material formed in the etched source region and the etched drain region.

A method of fabricating an integrated circuit including strained silicon bearing regions. The method forms a blanket layer of material having an initial thickness overlying a source region, a drain region, and a gate structure of an MOS device to cover an upper surface of the gate structure, including the hard mask layer, to form a substantially planarized surface region from the blanket layer. The method removes a portion of the initial thickness of the blanket layer to remove the hard mask and expose a portion of the gate structure. In a preferred embodiment, the portion of the gate structure is substantially polysilicon material. The method introduces dopant impurities into the portion of the gate structure using at least an implantation process to dope the gate structure, while maintaining the source region and the drain region free from the dopant impurities.

Polysilicon gate doping method and structure for strained silicon MOS transistors

A device structure and method for forming an interconnect structure in a magnetic random access memory (MRAM) device. In an exemplary embodiment, the method includes defining a magnetic stack layer on a lower metallization level, the magnetic stack layer including a non-ferromagnetic layer disposed between a pair of ferromagnetic layers. A conductive hardmask is defined over the magnetic stack layer, and selected portions of the hardmask and the magnetic stack layer, are then removed, thereby creating an array of magnetic tunnel junction (MTJ) stacks. The MTJ stacks include remaining portions of the magnetic stack layer and the hardmask, wherein the hardmask forms a self aligning contact between the magnetic stack layer and an upper metallization level subsequently formed above the MTJ stacks.

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Shanghai, China

Xian Jay Ning