Siemens Aktiengesellschaft

Infineon Technologies North America Corp.

International Business Machines Corporation

Xian J Ning

Rainer F Schnabel

Bruno Spuler

George Stojakovic

Nirmal Chaudhary

Xiaoming Yin

An all dry, low temperature process, for complete removal of organics and inorganic residues after metal etch of a microelectronic device comprising: rinsing a microelectronic device having a metallization layer after metal etch with a solution of ammonium hydroxide and hydrogen peroxide; subjecting the rinsed metallization layer to a low temperature GaSonics cleaning by exposing photoresist residue surface of the metallization layer to a fluorine containing reactive gas to form volatile compounds in the presence of a radio frequency input followed by photoresist stripping in an oxygen plasma at low temperature; subjecting the low temperature GaSonics treated residue surface to a gaseous SO,strip at low temperature to remove additional residue; and rinsing the SO,stripped material with de-ionized water to remove any remaining resist and residue.

Dry process for cleaning residues/polymers after metal etch

An improved method of forming a bond pad (222) by performing a dual damascene etch through a layer stack (200) disposed above a substrate (204) using self aligned vias (216). The layer (200) stack includes an underlying conductive layer (208) and an insulating layer (202) disposed above the underlying conductive layer (208). The method includes the following operative steps. At least a via hole (216) is formed in the insulating layer (202) positioned over the underlying device layer (208) and extending to the underlying device layer (208) at the bottom of the via hole. A bond pad trench (218) is then formed that takes the form of the desired bond pad (222). A layer of conductive material (220) is then placed over the insulating layer (202) substantially simultaneously filling the via hole (216) and the bond pad trench (218). The bond pad (222) is then formed by removing the layer of conductive material (220) sufficient to expose the upper surface of the insulating layer (210).

Dual damascene with bond pads

Methods for detecting under-etched vias, spaces, or under-polished portions in a wafer stack are disclosed. The wafer stack comprises a dielectric layer disposed on a metal layer. The dielectric layer has a plurality of vias etched therein. The wafer stack, including the plurality of vias, is exposed to an etchant which is configured to etch the metal layer at a substantially faster rate than the dielectric layer. As a result, cavities are formed in the metal layer below properly-etched vias. Then, the vias in the wafer stack are optically inspected to detect and identify under-etched vias, which reflect more light than the cavities etched into the metal layer.

Method for detecting under-etched vias

A substrate cleaning assembly (10) and method for removing contaminant substances (11) from a surface (12) of a substrate (13) employed in microelectronics manufacturing. The cleaning assembly (10) includes a substance locator (15) adapted to locate and map at least one contaminant substance (11) on the surface (12) of the substrate (13) and a dispenser (16) formed and dimensioned to accurately dispense a substantially controlled, impinging stream (17) of cleaning agent along a path (18). A controller (20) is coupled to the map device (15) and the dispenser (16), and is adapted to control the impinging stream (17) such that the located contaminant substance (11) is positioned in the path (18) of the impinging stream (17) to enable substantially localized impingement and removal of the substance (11) from the substrate surface (12).

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Mohegan Lake, NY, United States of America

Xian J Ning