Taiwan Semiconductor Manufacturing Comp. Ltd.

Wun-Jie Lin

Jam-Wem Lee

Yu-Ti Su

Jen-Chou Tseng

Kuo-Ji Chen

Han-Jen Yang

Bo-Ting Chen

Ming-Hsiang Song

Li-Wei Chu

Ching-Hsiung Lo

Sun-Jay Chang

Tao-Yi Hung

Yu-Hung Yeh

Min-Chang Liang

Chia-Wei Hsu

Wan-Yen Lin

Chien-Yao Huang

Tao Yi Hung

Arabinda Das

Stefan Rusu

Wen-Hao Chen

David Barry Scott

Yi-Feng Chang

Shui-Ming Cheng

Rabiul Islam

Po-Chia Lai

Shu-Yu Su

Chia-En Huang

Ming-Fu Tsai

Chia-Hui Chen

Shu-Yi Ying

Chien Yao Huang

Tzu-Hao Chiang

Kuan-Te Li

Cheng Hung Lee

Chia-Lin Hsu

Hong-Chen Cheng

Fu-An Wu

Chia-Jung Chang

Jung-Ping Yang

Chih-Chieh Chiu

Tsung-Che Tsai

Chin-Chi Wang

Hsiao-Lan Yang

Chang-Fen Hu

Wei-Shuo Kao

Wu-Ping Huang

Ling-Chang Hu

Jam-Wen Lee

Shou Ming Liu

An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.

Method and system for latch-up prevention

An integrated circuit (IC) device includes a plurality of first doped regions of a first semiconductor type over at least one first well region of the first semiconductor type, and a second doped region of a second semiconductor type over a second well region of the second semiconductor type. The second semiconductor type is different from the first semiconductor type. The plurality of first doped regions is arranged along a first direction. Each of the plurality of first doped regions has a first length in the first direction. The second doped region extends in the first direction between at least two first doped regions among the plurality of first doped regions over a second length greater than the first length.

Integrated circuit device and method

Devices, circuits, and methods for electrostatic discharge (ESD) protection are provided. An electrostatic discharge (ESD) protection circuit comprises a first transistor connected between a first voltage and a second voltage, and a first control circuit connected between the first voltage and the second voltage, and configured to supply a control signal to the first transistor. The circuit further comprises a second transistor connected between the second voltage and a third voltage, and a second control circuit connected between the second voltage and the third voltage, and configured to supply a control signal to the second transistor. The first control circuit and the second control circuit are connected to each other via a first interconnect and a second interconnect. The first and second transistors are configured to turn on in response to an ESD event.

ESD power clamp devices and circuits

A semiconductor device includes a first diode having a first cathode and a first anode, wherein the first cathode is floating. The semiconductor device includes a second diode having a second cathode and a second anode, wherein the first anode is coupled to the second anode with the second cathode connected to a first supply voltage. The semiconductor device includes a third diode having a third cathode and a third anode, wherein the third cathode is connected to the first anode at an input/output pin, with the third anode connected to a second supply voltage. The second anode is coupled to a circuit that is powered by the first supply voltage and the second supply voltage. The first diode has a first size and the second diode has a second size, and the first size is substantially greater than the second size.

Electrostatic discharge diodes with different sizes and methods of manufacturing thereof

An electrostatic discharge (ESD) protection circuit includes a first and second diode in a semiconductor wafer, an ESD clamp circuit and a first conductive structure on a backside of a semiconductor wafer. The first diode is coupled between an input output (IO) pad and a first node. The second diode is coupled to the first diode, and coupled between the IO pad and a second node. The ESD clamp circuit is in the semiconductor wafer, coupled to the first and second node, and between the first and second diode. The ESD clamp circuit includes a first signal tap region in the semiconductor wafer that is coupled to a reference voltage supply. The second diode is coupled to and configured to share the first signal tap region with the ESD clamp circuit. The first conductive structure is configured to provide a reference voltage to the first signal tap region.

Electrostatic discharge (ESD) protection circuit and method of operating the same

Systems and methods are provided for a self-biasing electro-static discharge (ESD) power clamp. The ESD power clamp comprises an ESD detection circuit coupled to a positive supply voltage node and a ground voltage node. The ESD detection circuit includes a first node having a first voltage level during a standby mode and a second voltage level during an ESD mode. The ESD power clamp further comprises a discharge circuit coupled to the ESD detection circuit that includes a plurality of discharge elements a self-biasing node having a third voltage level during the standby mode. The third voltage level provides a voltage drop across at least one of the discharge elements that is less than the first voltage level. The discharge circuit provides a high-impedance path during the standby mode and a low-impedance path during the ESD mode.

Self-biasing ESD power clamp

A snapback electrostatic discharge (ESD) protection circuit includes a first well in a substrate, a drain region of a transistor, a source region of the transistor, a gate region of the transistor, and a second well embedded in the first well. The first well has a first dopant type. The drain region is in the first well, and has a second dopant type different from the first dopant type. The source region is in the first well, has the second dopant type, and is separated from the drain region in a first direction. The gate region is over the first well and the substrate. The second well is embedded in the first well, and is adjacent to a portion of the drain region. The second well has the second dopant type.

Snapback electrostatic discharge (ESD) circuit, system and method of forming the same

In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.

Circuit and method for high voltage tolerant ESD protection

An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: an internal circuit patterned in a device wafer and electrically coupled between a first node and a second node, an array of electrostatic discharge (ESD) circuits patterned in a carrier wafer, where the ESD circuits are electrically coupled between a first node and a second node and configured to protect the internal circuit from transient ESD events, and where the device wafer is bonded to the carrier wafer.

Electrostatic discharge (ESD) array with back end of line (BEOL) connection in a carrier wafer

Capacitor cells are provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate directly connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate directly connected to the first node. A second PMOS transistor is coupled between the second node and the power supply, and has a gate directly connected to the second node. A second NMOS transistor is coupled between the first node and the ground, and has a gate directly connected to the first node. Sources of the first and second NMOS transistors share an N+ doped region in the P-type well region. The first NMOS transistor is disposed between the second NMOS transistor and the first and second PMOS transistors. Source of the first PMOS transistor is directly connected to the power supply.

Capacitor cell and structure thereof

A semiconductor device includes a substrate. The semiconductor device further includes a doped well in the substrate, wherein the doped well comprises a first concentration of dopants of a first type in the substrate. The semiconductor device further includes a doped region in the substrate, wherein the doped region comprises a second concentration of the dopants of the first type, the doped region extends around the doped well, and the doped region is electrically insulated from the doped well. The semiconductor device further includes an active area, and wherein the active area comprises an emitter region and a collector region, wherein the emitter region is electrically connected to the doped region. The semiconductor device further includes a deep trench isolation (DTI) structure extending through the active area and between the emitter region and the collector region.

Electrostatic discharge protection device and method of making

A method of making a semiconductor device includes manufacturing doped zones in a first semiconductor material over a substrate. The method further includes forming an isolation structure between adjacent doped zones of the first semiconductor material. The method further includes manufacturing lines extending in a first direction over the doped zones of the first semiconductor material, wherein each of the lines has a line width measured along a second direction perpendicular to the first direction. The method further includes trimming the lines into line segments having ends over the isolation structure. The method further includes etching a transistor gate electrode over the substrate, wherein transistor gate electrode has a gate electrode width measured along the second direction, and wherein the line width is substantially similar to the gate electrode width.

Method of making semiconductor device electrostatic discharge diode

An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: a plurality of transistors patterned on a semiconductor substrate during a front-end-of-line (FEOL) process, metal interconnects formed on top of the plurality of transistors during a back-end-of-line (BEOL) process and configured to interconnect the plurality of transistors, and a plurality of passive components formed under the semiconductor substrate in a backside layer during a backside a back-end-of-line (B-BEOL) process, wherein the plurality of passive components are connected to the plurality of transistors through a plurality of vias.

Electrical passive elements of an ESD power clamp in a backside back end of line (B-BEOL) process

A semiconductor device includes a device wafer having a first side and a second side. The first and second sides are opposite to each other. The semiconductor device includes a plurality of first interconnect structures disposed on the first side of the device wafer. The semiconductor device includes a plurality of second interconnect structures disposed on the second side of the device wafer. The plurality of second interconnect structures comprise a first power rail and a second power rail. The semiconductor device includes a carrier wafer disposed over the plurality of first interconnect structures. The semiconductor device includes an electrostatic discharge (ESD) protection circuit formed over a side of the carrier wafer. The ESD protection circuit is operatively coupled to the first and second power rails.

Electrostatic discharge circuit and method of forming the same

An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus comprises: an internal circuit formed in a first wafer; an array of electrostatic discharge (ESD) circuits formed in a second wafer, wherein the ESD circuits include a plurality of ESD protection devices each coupled to a corresponding switch and configured to protect the internal circuit from a transient ESD event; and a switch controller in the second wafer, wherein the switch controller is configured to control, based on a control signal from the first wafer, each of the plurality of ESD protection devices to be activated or deactivated by the corresponding switch, and wherein the first wafer is bonded to the second wafer.

Electrostatic discharge (ESD) array with circuit controlled switches

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Hsinchu, Taiwan

Wun-Jie Lin