Taiwan Semiconductor Manufacturing Comp. Ltd.

Macronix International Co., Ltd.

Wu-An Weng

Jiun-Rong Pai

Hsu-Shui Liu

Shou-Wen Kuo

Chien-Fa Lee

Sheng-Hsiang Chuang

Chien-Ko Liao

Chen-Chien Chang

Chia-Han Lin

Ya Hsun Hsueh

Becky Liao

Ethan Yu

Ming-Chi Tsai

Kuo-Yi Liu

Surendra Kumar Soni

Gary Tsai

Mei-Yun Wang

Shih-Chi Kuo

Chun-Chieh Mo

Tsung-Hsien Lee

Cheng-Chen Calvin Hsueh

Chung-Yu Lin

Kun-Yu Liu

Lee-Wei Yen

Wang-Tsai Hsu

Yi-Chieh Lai

Yaou-Dong Wang

Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.

Automated inspection tool

MRAM devices and methods of forming the same are provided. One of the MRAM devices includes a dielectric layer, a resistance variable memory cell and a conductive layer. The dielectric layer is over a substrate and has an opening. The resistance variable memory cell is in the opening and includes a first electrode, a second electrode and a magnetic tunnel junction layer between the first electrode and the second electrode. The conductive layer fills a remaining portion of the opening and is electrically connected to one of the first electrode and the second electrode of the resistance variable memory cell.

MRAM devices and methods of forming the same

The present disclosure provides a deep trench capacitor device. A first capacitor electrode is made up of a doped region of semiconductor substrate in which two or more trenches are arranged. A second capacitor electrode is made up of a continuous body of conductive material. The continuous body of conductive material includes a lower body portion filling the two or more trenches and an upper body portion extending continuously over the lower body portion. The upper body portion extends upwardly out of the trenches by a non-zero distance. A capacitor dielectric liner is arranged in the two or more trenches to separate the first and second capacitor electrodes. The capacitor dielectric liner extends continuously out of the two or more trenches along outer sidewalls of the upper body portion.

Deep trench capacitor manufactured by streamlined process

A method for forming a trench capacitor includes providing a substrate of a semiconductor material having a hard mask layer; etching the hard mask layer and the substrate to form at least one trench extending into the substrate; and performing pull-back etching on the hard mask layer. In the pull-back etching, a portion of the hard mask layer defining and adjacent to side walls of an opening of the at least one trench is removed. A resulting opening on the hard mask layer has a width dimension larger than a width dimension of an opening of the at least one trench extending into the substrate. The method further comprises doping the semiconductor material defining upper surfaces and sidewalls of the at least one trench to form a doped well region.

Self-aligned deep trench capacitor, and method for making the same

The present disclosure provides a streamlined approach to forming vertically structured devices such as deep trench capacitors. Trenches and a contact plate bridging the trenches are formed using one lithographic process. A hard mask is formed over the substrate and etched through the mask to form two or more closely spaced trenches. The hard mask is then reduced by an isotropic etch process. The etch removes the hard mask preferentially between the trenches. Chemical mechanical polishing removes the conductive material down to the remaining hard mask layer, whereby conductive material remains in mask openings and forms a conductive bridge across the trenches.

Streamlined process for vertical semiconductor devices

Semiconductor devices with selective stress memory effect and fabrication methods thereof. The semiconductor device comprises a semiconductor substrate with a first region and a second region. Both the first region and the second region have a first doped region and a second doped region separated by an insulation layer. A PMOS transistor is disposed on the first doped region layer. An NMOS transistor is disposed on the second doped region. A first capping layer is disposed covering the NMOS transistor over the first region. A second capping layer is disposed covering the PMOS transistor over the first region. The thickness of the first capping layer is different from the thickness of the second capping layer, thereby different stress is induced on the PMOS transistor and the NMOS transistor respectively. The PMOS transistor and the NMOS transistor over the second region are silicided.

Integrated circuits with stress memory effect and fabrication methods thereof

The invention describes a method to facilitate the use of low-sensitivity monitoring equipment for detecting and monitoring defects on the surface of semiconductor wafers. The method includes the use of a hydrofluoric acid solution for increasing the dimensions of a defect and the application of a thin-film layer of a metal, such as titanium, for improving the appearance of the defect such that the defect dimensions increase to above 0.1 nanometer, the detection threshold for economical low-sensitivity monitoring equipment.

Monitoring semiconductor wafer defects below one nanometer

A method for fabricating a capacitor in a semiconductor device that includes providing a semiconductor substrate, forming at least one shallow trench isolation structure in the semiconductor substrate, forming a tunnel oxide layer over the semiconductor substrate, depositing a first polysilicon layer over the tunnel oxide layer, depositing a nitride layer over the first polysilicon layer, depositing a first photoresist over the nitride layer, patterning and defining the first photoresist layer to expose at least a portion of the nitride layer, etching the exposed portion of the nitride layer and the first polysilicon layer underneath the exposed portion of the nitride layer to expose at least a portion of the tunnel oxide layer, removing the patterned and defined photoresist layer, forming a second oxide layer over at least the exposed portion of the tunnel oxide layer, providing a second photoresist layer over the second oxide layer, providing an etchback process to remove a portion of the second photoresist layer and a potion of the nitride layer, removing the residual second photoresist layer and the residual nitride layer to expose at least a portion of the first polysilicon layer, and forming and patterning a second polysilicon layer over at least the exposed portion of the first polysilicon layer.

Method for fabricating a capacitor in a semiconductor device

Alignment structures in gaps between patterned features, such as polysilicon wordlines or metal contacts, have a selective effect on various processes to promote self-alignment. The various processes include ion implants for code programming, formation of via cuts, and the polycide process of forming composite layered gates. The alignment structures improve these processes by having a selective effect during etching, deposition, and ion implants. Thus, in one example, to prepare a ROM array for code programming using the ion implantation process, the alignment structures or ion barrier walls are formed between the plurality of wordlines. These ion barrier walls, typically silicon nitride or silicon dioxide, have a height above the substrate that is greater than the height of the wordlines. When viewed from a direction orthogonal to the substrate, only the ion barrier walls and wordlines are visible. Thus, despite mask misalignment or critical dimension variations, the ion barrier walls increase the process window for the code programming step of the mask ROM manufacturing process, minimize code programming or ion implant errors, and facilitate ion implant alignment in selected channel regions to provide uniform channel widths among similarly coded channel regions. Furthermore, the ion barrier walls provide additional contact and support surface area for the mask.

Integrated circuit self-aligning process and apparatus

A high performance and high density integrated circuit includes interbank bitlines and a bank select structure which improve the vertical pitch of the integrated circuit layout and provide the selective access of data stored in the memory cells. The bank select structures includes bank select transistors which are located and oriented adjacent metal-to-diffusion region contacts such that vertical pitch of the layout is improved, thus promoting a higher density memory array. The bank select transistor is also formed such that conductivity is increased and impedance decreased due to a relatively wide channel width. On the substrate, a plurality of bitlines, including interbank bitlines and intrabank bitlines, and a plurality of wordlines are provided to form memory cells. In bank BK.sub.N, each interbank bitline extends into either bank BK.sub.N-1 or BK.sub.N+1 adjacent to bank BK.sub.N. For the selection of a cell or plurality of cells in bank BK.sub.N, bank BK.sub.N is selected first by applying bank select signals B.sub.N and B.sub.N+1 to bank select lines BSL.sub.N and BSL.sub.N+1, respectively, which activate respective bank select transistors. The desired column is selected by turning on respective column select transistors which are coupled to the sense amplifiers and readout circuits via column select lines and applying decode voltages to the selected column via the activated bank select transistors. Finally, the desired memory cell or cells within that selected column and bank BK.sub.N is selected with the plurality of left-right bit selector lines.

Growing community of inventors

Hsinchu, Taiwan

Wu-An Weng