Samsung Electronics Co., Ltd.

Samsung Sdi Co., Inc.

Woo-Jin Kim

Se-Chung Oh

Jeong-Heon Park

Whan-Kyun Kim

Jang-Eun Lee

Hee-Ju Shin

Young-Hyun Kim

Joon-Myoung Lee

Hee-Seong Lee

Jun-Ho Jeong

Jun-ho Jeong

Woo-chang Lim

Deok-Hyeon Kang

Hyun Min Cho

Jae-Hoon Kim

Yong-Sung Park

Im-Su Choi

Yun-Jae Lee

Nak Hee Seong

Soo-Jin Lee

Shin-Hee Han

Nak-Hee Seong

Woo-Chang Lim

Sang Woo Kim

Gwan-Hyeob Koh

Yoon-jong Song

Suk-Hun Choi

Byung-Jun Min

Jeong-Ho Bang

Yong-Hwan Ryu

Kyung-tae Nam

Ki-seok Suh

Seung-yeol Lee

Ken Tokashiki

Kyoung-Sun Kim

Jung-Hoon Bak

Yun Ju Kwon

Ki-Woong Kim

Joon-Woo Cho

Sang-hwan Park

Jae-Il Lee

Hyun-Seop Shim

Ki-woong Kim

Yoon-Phil Eo

Dae-Kyom Kim

Geun-Yeong Chang

Seung-Woo Chang

Yoon-Sung Han

Jea-Hyoung Lee

Chee-Young Yoon

Young-Chan Lee

Mina Lee

Hyun-Geun Iy

A method of manufacturing an MRAM device, the method including forming a first magnetic layer on a substrate; forming a first tunnel barrier layer on the first magnetic layer such that the first tunnel barrier layer includes a first metal oxide, the first metal oxide being formed by oxidizing a first metal layer at a first temperature; forming a second tunnel barrier layer on the first tunnel barrier layer such that the second tunnel barrier layer includes a second metal oxide, the second metal oxide being formed by oxidizing a second metal layer at a second temperature that is greater than the first temperature; and forming a second magnetic layer on the second tunnel barrier layer.

Magnetoresistive random access memory (MRAM) device

A MRAM device includes a first insulating interlayer on a substrate including a cell region and a peripheral region, lower electrode contacts extending through the first insulating interlayer of the cell region, a first structure on each of the lower electrode contacts, the first structure including a lower electrode, a magnetic tunnel junction structure, and an upper electrode sequentially stacked, and a capping layer covering surfaces of the first insulating interlayer and the first structure in the cell and peripheral regions, wherein an upper surface of the capping layer on the first insulating interlayer in the peripheral region is higher than an upper surface of the capping layer on the first insulating interlayer between the first structures in the cell region.

Method of manufacturing magnetoresistive random access memory device

Magnetoresistive random access memory device

Method of manufacturing a magnetoresistive random access memory device

A bus system is provided. A bus system includes a slave functional block and a master functional block. The master functional block transmits a first command to the slave functional block. The slave functional block includes a first bus protector. The first bus protector receives the first command on behalf of the slave functional block and transmits a dummy signal corresponding to the first command to the master functional block in response to the slave functional block being in a state of not being able to receive the first command or not being able to transmit a response signal corresponding to the first command.

Bus system

The methods of manufacturing an MRAM device and MRAM devices are provided. The methods may include forming a first electrode on an upper surface of a substrate, forming a first magnetic layer on the first electrode, forming a tunnel barrier structure on the first magnetic layer, forming a second magnetic layer on the tunnel barrier structure, and forming a second electrode on the second magnetic layer. The tunnel barrier structure may include a first tunnel barrier layer and a second tunnel barrier layer that are sequentially stacked on the first magnetic layer and may have different resistivity distributions from each other along a horizontal direction that may be parallel to the upper surface of the substrate.

Magnetoresistive random access memory devices and methods of manufacturing the same

A system-on-chip (SoC) may include a master, a slave, and an asynchronous interface having a first first-in first-out (FIFO) memory connected to the master and the slave. A write operation of the FIFO memory is controlled based upon a comparison of a write pointer and an expected write pointer of the FIFO memory, and a read operation of the FIFO memory is controlled based upon a comparison of a read pointer and an expected read pointer of the FIFO.

System-on-chip including asynchronous interface and driving method thereof

An MRAM device may include an insulating interlayer structure, a lower electrode contact structure and a variable resistance structure. The insulating interlayer may be formed on a substrate. The lower electrode contact structure may extend through the insulating interlayer. The lower electrode contact structure may include a first electrode having a pillar shape and a second electrode having a cylindrical shape on the first electrode. An upper surface of the second electrode may have a ring shape. A variable resistance structure may be formed on the second electrode. The variable resistance structure may include a lower electrode, a magnetic tunnel junction (MTJ) structure and an upper electrode sequentially stacked.

Magnetoresistive random access memory device and method of manufacturing the same

A magnetic tunnel junction (MTJ) structure includes a fixed layer pattern structure having a perpendicular magnetization direction, a tunnel barrier pattern on the fixed layer pattern structure, a free layer pattern on the tunnel barrier pattern, the free layer pattern having a perpendicular magnetization direction, a first surface magnetism induction pattern on the free layer pattern, the first surface magnetism induction pattern inducing a perpendicular magnetism in a surface of the free layer pattern, a conductive pattern on the first surface magnetism induction pattern, and a ferromagnetic pattern on the conductive pattern.

MTJ structures including magnetism induction pattern and magnetoresistive random access memory devices including the same

A mobile system includes a first interface configured to transmit a payload in synchronization with a first clock signal through a first channel at a first transfer rate; and a second interface that includes: a payload storage connected to the first channel and configured to receive the payload from the first channel; and a payload receiver connected to the payload storage and configured to receive the payload from the payload storage in synchronization with a second clock at a second transfer rate through a second channel. A length of the second channel is shorter than a length of the first channel, and the first clock signal is asynchronous with the second clock signal.

Asynchronous interface in a system on chip and a method of operating the same

A semiconductor device is provided having a free layer and a pinned layer spaced apart from each other. A tunnel barrier layer is formed between the free layer and the pinned layer. The pinned layer may include a lower pinned layer, and an upper pinned layer spaced apart from the lower pinned layer. A spacer may be formed between the lower pinned layer and the upper pinned layer. A non-magnetic junction layer may be disposed adjacent to the spacer or between layers in the upper or lower pinned layer.

Semiconductor device having pinned layer with enhanced thermal endurance

In a method of manufacturing a MRAM device, a lower electrode is formed on a substrate. A first magnetic layer, a tunnel barrier layer, and a second magnetic layer are sequentially formed on the lower electrode layer. An etching mask is formed on the second magnetic layer. An ion beam etching process in which a first ion beam and a second ion beam are simultaneously emitted onto the substrate is performed to form a MTJ structure including a first magnetic layer pattern, a tunnel layer pattern, and a second magnetic layer pattern from the first magnetic layer, the tunnel barrier layer, and the second magnetic layer, respectively, the MTJ structure has no by-products remaining after the ion beam etching process is performed.

Methods of manufacturing a magnetoresistive random access memory device

Growing community of inventors

Yongin-si, South Korea

Woo-Jin Kim