Hyundai Electronics Industries Co. Ltd.

Lg Semicon Co., Ltd.

Won-Suck Yang

Chang-Jae Lee

A memory cell structure for a semiconductor memory device and fabricating method thereof, which is suitable for DRAM memory devices of 256M or more capacity requiring a very high degree of integration, which comprises the steps of forming sequentially first and second random layers on a semiconductor substrate; patterning a first photoresist layer having a limited line width on the second random layer; patterning the second random layer using as a mask the patterned first photoresist layer; removing the first photoresist layer, and then patterning the second photoresist layer having the limited line width between the pattern of the second random layer; patterning the first random layer using as a mask the second photoresist layer which is so patterned so as to be placed between the pattern of the second random layer; and removing the second random layer and the second photoresist layer.

Growing community of inventors

Cheongju, South Korea

Won-Suck Yang