Freescale Semiconductor,inc.

Nxp Usa, Inc.

Won Gi Min

Jiang-kai Zuo

Hongning Yang

Zhihong Zhang

Veronique C Macary

Robert W Baird

Gordon P Lee

Hongzhong Xu

Xin Lin

Daniel J Blomberg

Geoffrey W Perkins

Xu Cheng

Kyle Zukowski

Pete Rodriquez

Jiangkai Zuo

Amanda M Kroll

Geno L Fallico

John L Huber

A device includes a semiconductor substrate, a first constituent transistor including a first plurality of transistor structures in the semiconductor substrate connected in parallel with one another, and a second constituent transistor including a second plurality of transistor structures in the semiconductor substrate connected in parallel with one another. The first and second constituent transistors are disposed laterally adjacent to one another and connected in parallel with one another. Each transistor structure of the first plurality of transistor structures has a lower resistance in a saturation region of operation than each transistor structure of the second plurality of transistor structures.

Composite semiconductor device with different channel widths

The embodiments described herein provide an antifuse that includes a substrate material and an isolation trench formed in the substrate material, where the isolation trench has a first side and a second side opposite the first side. An electrode is positioned above the substrate material and proximate to the first side of the isolation trench. An insulating layer is disposed between the electrode and the substrate material. So configured, a voltage or current applied between the electrode and the substrate material causes a rupture in the insulating layer and creates a current path through the insulating layer and under the isolation trench to the substrate material proximate the second side of the isolation trench.

Fast programming antifuse and method of manufacture

Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices, e.g., LDMOS transistors, by careful charge balancing, even when body and drift region charge balance is not ideal, by: (i) providing a plug or sinker near the drain and of the same conductivity type extending through the drift region at least into the underlying body region, and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall coupled to the device buried layer, and/or (iii) providing a variable resistance bridge between the isolation wall and the drift region. The bridge may be a FET whose source-drain couple the isolation wall and drift region and whose gate receives control voltage Vc, or a resistor whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer via the isolation wall.

Resurf semiconductor device charge balancing

A device includes a semiconductor substrate, a drift region in the semiconductor substrate and having a first conductivity type, an isolation region within the drift region, and around which charge carriers drift on a path through the drift region during operation, and a protection region adjacent the isolation region in the semiconductor substrate, having a second conductivity type, and disposed along a surface of the semiconductor substrate.

Semiconductor device with HCI protection region

A method of fabricating a transistor includes forming a field isolation region in a substrate. After forming the field isolation region, dopant is implanted in a first region of a substrate for formation of a drift region. A drain region is formed in a second region of the substrate. The first and second regions laterally overlap to define a conduction path for the transistor. The first region does not extend laterally across the second region.

Drain-end drift diminution in semiconductor devices

RESURF semiconductor device charge balancing

A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate, a channel region in the semiconductor substrate between the source and drain regions through which charge carriers flow during operation from the source region to the drain region, and a drift region in the semiconductor substrate, on which the drain region is disposed, and through which the charge carriers drift under an electric field arising from application of a bias voltage between the source and drain regions. A PN junction along the drift region includes a first section at the drain region and a second section not at the drain region. The drift region has a lateral profile that varies such that the first section of the PN junction is shallower than the second section of the PN junction.

Semiconductor device with drain-end drift diminution

Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices (), e.g., LDMOS transistors, by careful charge balancing, even when body () and drift () region charge balance is not ideal, by: (i) providing a plug or sinker () near the drain () and of the same conductivity type extending through the drift region () at least into the underlying body region (), and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall () coupled to the device buried layer (), and/or (iii) providing a variable resistance bridge () between the isolation wall () and the drift region (). The bridge () may be a FET () whose source-drain () couple the isolation wall () and drift region () and whose gate () receives control voltage Vc, or a resistor () whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer () via the isolation wall ().

Methods are disclosed for forming an antifuse that includes first and second conductive regions having spaced-apart curved portions, with a first dielectric region therebetween, forming in combination with the curved portions a curved breakdown region adapted to switch from a substantially non-conductive initial state to a substantially conductive final state in response to a predetermined programming voltage. A sense voltage less than the programming voltage is used to determine the state of the antifuse as either OFF (high impedance) or ON (low impedance). A shallow trench isolation (STI) region is desirably provided adjacent the breakdown region to inhibit heat loss from the breakdown region during programming. Lower programming voltages and currents are observed compared to antifuses using substantially planar dielectric regions. In a further embodiment, a resistive region is inserted in one lead of the antifuse with either planar or curved breakdown regions to improve post-programming sense reliability.

Methods for forming antifuses with curved breakdown regions

A semiconductor device includes a source region within a semiconductor substrate, a drain region within the semiconductor substrate, a control gate over the semiconductor substrate and between the source region and the drain region, a first gate between the control gate and the drain region, and a first doped region within the semiconductor region and between the control gate and the first gate. The method of forming the semiconductor device may include depositing an electrode material over the semiconductor substrate, patterning the electrode material to form a control gate and a first gate, implanting a first doped region within the semiconductor substrate between the control gate and the first gate while using the control gate and the first gate as a mask, and implanting a source region within the semiconductor substrate.

Laterally diffused metal oxide semiconductor (LDMOS) device with multiple gates and doped regions

An antifuse (') comprises, first () and second (&#x2032;) conductive regions having spaced-apart curved portions (), with a first dielectric region () therebetween, forming in combination with the curved portions () a curved breakdown region () adapted to switch from a substantially non-conductive initial state to a substantially conductive final state in response to a predetermined programming voltage. A sense voltage less than the programming voltage is used to determine the state of the antifuse as either OFF (high impedance) or ON (low impedance). A shallow trench isolation (STI) region () is desirably provided adjacent the breakdown region () to inhibit heat loss from the breakdown region () during programming. Lower programming voltages and currents are observed compared to antifuses () using substantially planar dielectric regions (). In a further embodiment, a resistive region () is inserted in one lead (&#x2032;) of the antifuses (&#x2032;) with either planar () or curved () breakdown regions to improve post-programming sense reliability.

Antifuses with curved breakdown regions

An antifuse element () includes a substrate material () having an active area () formed in an upper surface, a gate electrode () having at least a portion positioned above the active area (), and a gate oxide layer () disposed between the gate electrode () and the active area (). The gate oxide layer () includes one of a gate oxide dip () or a gate oxide undercut (). During operation a voltage applied between the gate electrode () and the active area () creates a current path through the gate oxide layer () and a rupture of the gate oxide layer () in a rupture region (). The rupture region () is defined by the oxide structure and the gate oxide dip () or the gate oxide undercut ().

Antifuse elements

An embodiment of an N-channel device has a lightly doped substrate in which adjacent or spaced-apart P and N wells are provided. A lateral isolation wall surrounds at least a portion of the substrate and is spaced apart from the wells. A first gate overlies the P well or the substrate between the wells or partly both. A second gate, spaced apart from the first gate, overlies the N-well. A body contact to the substrate is spaced apart from the isolation wall by a first distance within the space charge region of the substrate to isolation wall PN junction. When the body contact is connected to the second gate, a predetermined static bias Vgis provided to the second gate, depending upon the isolation wall bias (Vbias) and the first distance.

Dual gate LDMOS devices

Embodiments of microelectronic assemblies are provided. First and second semiconductor devices are formed over a substrate having a first dopant type at a first concentration. First and second buried regions having a second dopant type are formed respectively below the first and second semiconductor devices with a gap therebetween. At least one well region is formed over the substrate and between the first and second semiconductor devices. A barrier region having the first dopant type at a second concentration is formed between and adjacent to the first and second buried regions such that at least a portion of the barrier region extends a depth from the first and second semiconductor devices that is greater or equal to the depth of the buried regions.

Microelectronic assemblies with improved isolation voltage performance

A method for forming a microelectronic assembly and a microelectronic assembly are provided. First and second semiconductor devices () are formed over a substrate () having a first dopant type at a first concentration. First and second buried regions () having a second dopant type are formed respectively below the first and second semiconductor devices with a gap () therebetween. At least one well region () is formed over the substrate and between the first and second semiconductor devices. A barrier region () having the first dopant type at a second concentration is formed between and adjacent to the first and second buried regions such that at least a portion of the barrier region extends a depth () from the first and second semiconductor devices that is greater or equal to the depth of the buried regions.

Growing community of inventors

Chandler, AZ, United States of America

Won Gi Min