International Business Machines Corporation

Globalfoundries Inc.

Marvell Asia Pte., Ltd.

Marvell International Limited

Ultratech, Inc.

Wolfgang Sauter

Christopher David Muzzy

Jeffrey P Gambino

Timothy Harrison Daubenspeck

Timothy Dooling Sullivan

Charles Leon Arvin

David L Questad

Edmund Juris Sprogis

Eric D Perfecto

Thomas Anthony Wassick

Ekta Misra

Eric W Tremble

Zhong-Xiang He

Kevin Shawn Petrarca

Mark William Kuemerle

Jeffrey Scott Zimmerman

Richard Paul Volant

Brian Michael Erwin

Marie-Claude Paquet

Charles F Musante

Louis L Hsu

Robert K Leidy

David Brian Stone

William Thomas Motsiff

George John Scott

Lloyd G Burrell

Albert J Banach

Caitlin W Weinstein

Anthony K Stamper

Steven H Voldman

Timothy Joseph Dalton

Mark David Jaffe

Douglas Duane Coolbaugh

Kerry Bernstein

Jon Alfred Casey

Raschid Jose Bezama

Roger Allan Quon

Wayne Harvey Woods, Jr

Steven Lorenz Wright

Jerome Brett Lasky

Takashi Hisada

Brian Richard Sundlof

Douglas Oliver Powell

Sarah Huffsmith Knickerbocker

Kamalesh K Srivastava

Howard Hao Chen

Stephen Peter Ayotte

Ian D Melville

Peter Jeffrey Brofman

Tien-Jen Cheng

Anson Jay Call

Ephrem G Gebreselasie

Randolph F Knarr

Jonathan H Griffith

Paul Marian Harvey

Yaping Zhou

Lisa A Fanti

David E Eichstadt

Ashwani K Malhotra

Samuel McKnight

Charles F Carey

David Angell

Barbara Ann Waterhouse

Erwin B Cohen

Jennifer D Schuler

Frederic Beaulieu

Julie C Biggs

Adreanne Kelly

Dany Minier

Bernt Julius Hansen

Hiromitsu Miyai

Mukta G Farooq

James William Adkisson

Hanyi Ding

David John Russell

Minhua Lu

Paul Francis Fortier

Krystyna Waleria Semkow

Toyohiro Aoki

Guoan Wang

Timothy Charles Krywanczyk

Thomas Edward Lombardi

Nicholas A Polomoff

Edmund D Blackshear

Hung H Tran

Daniel W Storaska

Steven E Molis

Ze Zhang

John Chester Malinowski

Michael J Hauser

Edward R Pillai

Steven Ross Codding

Karen P McLaughlin

Douglas M Daley

Gordon C Osborne, Jr

John Jay Maloney

Joseph D Danaher

Nathalie Normand

Seungman Choi

James R Palmer

An electronic network device includes: (i) an integrated circuit (IC) die configured to exchange signals between the electronic network device and one or more other devices that are remote from the electronic network device, (ii) a plurality of transceiver dies, separate from the IC die, the plurality of transceiver dies being disposed along at least a first axis extending at an acute angle from an edge of the IC die and intersecting the edge at a first point, the transceiver dies being configured to exchange the signals between the IC die and the other devices, and (iii) electrical connections configured to connect between the IC die and at least one of the transceiver dies for exchanging at least some of the signals between the IC die and the transceiver dies.

Lateral escape using triangular structure of transceivers

The present disclosure relates to semiconductor structures and, more particularly, to partitioned substrates with interconnect bridge structures and methods of manufacture. The structure includes: a plurality of substrates; at least one chip bonded and electrically connected to each of the plurality of substrates; and an interconnect bridge that physically connects the plurality of substrates and electrically connects each of the plurality of chips bonded to each of the plurality of substrates.

Partitioned substrates with interconnect bridge

A pillar-type connection includes a first conductive layer that includes a hollow core. A second conductive layer is connected to the first conductive layer defining a conductive pillar that includes a top surface defining a recess aligned with the hollow core.

Conductive pillar shaped for solder confinement

Disclosed is a multi-chip module (MCM) with redundant chip-to-chip communication connection(s) to minimize the need to discard a chip-mounting layer due to defective signal traces. The MCM includes at least first and second chips mounted on the chip-mounting layer. The chip-mounting layer includes signal traces that are electrically connected between first and second links on the first and second chips, respectively, to form communication connections including at least one redundant communication connection. Instead of being directly connected to the chip-to-chip communication connections, first and second interfaces on the first and second chips are connected via first and second multiplexors, respectively, to selected ones of multiple chip-to-chip communication connections. By employing the multiplexors and the redundant chip-to-chip communication connection(s), chip-to-chip communication connection(s) with defective signal trace(s) can be bypassed. Specifically, during MCM assembly, the multiplexors are programmed to avoid using chip-to-chip communication connections with defective signal traces.

Multi-chip module (MCM) with chip-to-chip connection redundancy and method

An IC chip structure including a plurality of IC chips electrically connected to one another in back-end-of-line (BEOL) interconnect layer of the structure is disclosed. The IC structure may include openings in crack-stop structures surrounding the IC chips and a interconnect wire extending between the IC chips through the openings. A packaging structure for utilizing the IC structure where at least one IC chip is inoperable is also disclosed. The structure may include a first bond pad array on a top surface of a packaging substrate including operable bond pads connected to an operable IC chip and structural support bond pads connected to the inoperable IC chip; a second bond pad array on a bottom surface of the substrate including operable bond pads connected to a single IC chip printed circuit board; and an interconnect structure for connecting the operable bond pads of the first and second bond pad arrays.

Interconnected integrated circuit (IC) chip structure and packaging and method of forming same

A method of manufacturing a bond pad structure may include depositing an aluminum-copper (Al&#x2014;Cu) layer over a dielectric layer; and depositing an aluminum-chromium (Al&#x2014;Cr) layer directly over the Al&#x2014;Cu layer.

Corrosion resistant aluminum bond pad structure

A pillar-type connection includes a first conductive layer that includes a hollow core. A second conductive layer is connected to the first conductive layer defining a conductive pillar that includes a top surface defining a recess aligned with the hollow core. A conductive via terminates at a top surface of the first conductive layer.

A multi-chip module, and method of fabricating the multi-chip module. The multi-chip module includes: a substrate containing multiple wiring layers, each wiring layer having first pads on a top surface of the substrate and second pads on a bottom surface of the substrate, wherein the second pads include split pad and a conventional pad; a first solder ball in direct physical contact with a contiguous bottom surface of the conventional pad and connected to a next level of packaging under the conventional pad, wherein the first solder ball has a first height; and a second solder ball in direct physical contact with first and second sections of the split pad separated by a gap, wherein the second solder ball has a second height that is sufficiently less than the first height such that the second solder ball is not connected to the next level of packaging.

Split ball grid array pad for multi-chip modules

The present disclosure relates to semiconductor structures and, more particularly, to photonics chips and methods of manufacture. A structure includes: a photonics chip having a grated optical coupler; an interposer attached to the photonics chip, the interposer having a grated optical coupler; an optical epoxy material provided between the grated optical coupler of the photonics chip and the grated optical coupler of the interposer; and epoxy underfill material provided at interstitial regions between the photonics chip and the interposer which lie outside of an area of the grated optical couplers of the photonics chip and the interposer.

Photonics chip

A method of fabricating a pillar-type connection includes forming a second conductive layer on a first conductive layer to define a conductive pillar that includes a non-planar top surface defining a recess aligned with a hollow core of the first conductive layer.

A method of fabricating a pillar-type connection includes forming a first conductive layer. A second conductive layer is formed on the first conductive layer to define a conductive pillar that includes a top surface defining a recess aligned with a hollow core of the first conductive layer. A conductive via that terminates at a top surface of the first conductive layer is formed.

A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process.

Structures and methods to enable a full intermetallic interconnect

An embodiment of the invention may include a semiconductor structure, and method of forming the semiconductor structure. The semiconductor structure may include a first set of pillars located on a first substrate. The semiconductor structure may include a second set of pillars located on a second substrate. The semiconductor structure may include a joining layer connecting the first pillar to the second pillar. The semiconductor structure may include an underfill layer located between the first and second substrate.

Nanowires for pillar interconnects

Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, an interconnect structure can include: a photosensitive polyimide (PSPI) layer including a pedestal portion; a controlled collapse chip connection (C4) bump overlying the pedestal portion of the PSPI layer; a solder overlying the C4 bump and contacting a side of the C4 bump; and an underfill layer abutting the pedestal portion of the PSPI and the C4 bump, wherein the underfill layer and the solder form a first interface separated from the PSPI pedestal.

Extrusion-resistant solder interconnect structures and methods of forming

Growing community of inventors

Richmond, VT, United States of America

Wolfgang Sauter