Intel Corporation

Infineon Technologies Ag

Apple Inc.

Wolfgang Molzer

Reinhard Mahnkopf

Hans-Joachim Barth

Georg Seidemann

Sven Albers

Edmund Goetz

Bernd Memmler

Thorsten Meyer

Harald Gossner

Bernd Waidhas

Domagoj Siprak

Uwe Hodel

Giovanni Calabrese

Thomas Wagner

Wolfgang Klein

Rudolf Lachner

Michael P Skinner

Kenan Kocagoez

Jose Cesares Cano

Stephan Stoeckl

Sven Dortmund

Teodora Ossiander

Martin Ostermayr

Christian Mueller

Matthias Obermeier

Michael Langenbuch

Klaus Herold

Joachim Singer

IC devices including BPRs with integrated decoupling capacitance are disclosed. An example IC device includes a first layer comprising a transistor and a support structure adjoining the first layer. The support structure includes BPRs, which are power rails buried in the support structure, and a decoupling capacitor based on the BPRs. The conductive cores of the BPRs are the electrodes of the decoupling capacitor. The dielectric barriers of the BPRs can be the dielectric of the decupling capacitor. The dielectric of the decupling capacitor may also include a dielectric element between the BPRs. Additionally or alternatively, the IC device includes another decoupling capacitor at the backside of the support structure. The other decoupling capacitor is coupled to the BPRs and can provide additional decoupling capacitance for stabilizing power supply facilitated by the BPRs.

Buried power rails integrated with decoupling capacitance

Embodiments disclosed herein include semiconductor packages. In a particular embodiment, the semiconductor package is a wafer level chip scale package (WLCSP). In an embodiment, the WLCSP comprises a die. In an embodiment, the die comprises an active surface and a backside surface. The die has a first coefficient of thermal expansion (CTE). In an embodiment, the WLCSP further comprises a channel into the die. In an embodiment, the channel is filled with a stress relief material, where the stress relief material has a second CTE that is greater than the first CTE.

Stress relief die implementation

A method () for temperature control in a radio receiver includes: receiving () a sequence of radio subframes, wherein each radio subframe () in the sequence of radio subframes comprises at least one control region () and at least one data region (); monitoring () temperature information indicating a system temperature (T) of the radio receiver; and if the temperature information indicates that the system temperature (T) exceeds () a first threshold (T), transition () to a second state () in which receiving the at least one data region is disabled.

Method and device for temperature control in a radio receiver

Disclosed herein are Lateral Diffused Metal Oxide Semiconductor (LDMOS) device and trench isolation related devices, methods, and techniques. In one illustration, a doped region is formed within a semiconductor substrate. A trench isolation region is formed within the doped region. The doped region and the trench isolation region are part of a Lateral Diffused Metal Oxide Semiconductor (LDMOS) device. The trench isolation region or an interface between the trench isolation region and the doped region is configured to reduce low frequency noise in the LDMOS device.

Methods of forming low noise semiconductor devices

Embodiments of the present description include stacked microelectronic dice embedded in a microelectronic substrate and methods of fabricating the same. In one embodiment, at least one first microelectronic die is attached to a second microelectronic die, wherein an underfill material is provided between the second microelectronic die and the at least one first microelectronic die. The microelectronic substrate is then formed by laminating the first microelectronic die and the second microelectronic die in a substrate material.

Methods of forming stacked microelectronic dice embedded in a microelectronic substrate

Stacked microelectronic dice embedded in a microelectronic substrate

Via are described for radio frequency antenna connections related to a package. In one example, a package has a package substrate, a die attached to the package substrate, and a conductive via from the package substrate to an external surface of the package to make a radio frequency connection between the antenna and the package substrate.

Package vias for radio frequency antenna connections

An apparatus comprises a first integrated circuit (IC) die that includes a top layer, a bottom surface, a sidewall surface extending from a top surface of the top layer to the bottom surface, and at least one multi-surface contact pad, a second IC die including a top layer, a bottom surface, a sidewall surface extending from a top surface of the top layer to the bottom surface, and at least one multi-surface contact pad, wherein the second IC die is arranged adjacent to the first IC die, and includes an electrically conductive bond in contact with at least one of the top surface or the side surface of the multi-surface contact pad of the first IC die and the top surface of the multi-surface contact pad of the second IC die.

Die edge side connection

Semiconductor devices may be configured to reduce noise in the devices. For example, a semiconductor device may be configured or made with a first doped region within a semiconductor substrate to operate as an extended drain region, a trench isolation region, a second doped region between the first doped region and the trench isolation region, wherein the trench isolation region and the second doped region may be at least partially formed within the first doped region. Additionally, or alternatively, the second doped region may be within the first doped region and at least partially surround the trench isolation region, the first and second doped regions may have the same conductivity type, and the second doped region may have a higher conductivity than the first doped region.

Low noise semiconductor devices

A silicon-germanium bipolar transistor includes a silicon substrate in which a first n-doped emitter region, a second p-doped base region adjoining the latter and a third n-doped collector region adjoining the latter, are formed. A first space charge zone is formed between the emitter region and the base region and a second space charge zone is formed between the base region and the collector region. The base region and an edge zone of the adjoining emitter region are alloyed with germanium. The germanium concentration in the emitter region rises toward the base region. The germanium concentration in a junction region containing the first space charge zone rises less sharply than in the emitter region or decreases and, in the base region, it initially again rises more sharply than in the junction region.

Silicon-germanium bipolar transistor with optimized germanium profile

Growing community of inventors

Ottobrunn, Germany

Wolfgang Molzer