International Business Machines Corporation

Wolfgang Euen

Dieter Hagmann

Hans-Jurgen Wildau

Hans-Joachim Trumpp

Disclosed is a thin dielectric inorganic layer overlaying a substrate, and having a thickness of.ltoreq. about 20 nm and a defect density of.ltoreq. about 0.6 defects/cm.sup.2 determined by BV measurements. Also disclosed is a method of forming such a layer, according to which a layer having the desired composition and thickness is formed on a substrate, followed by an ion implantation into the substrate through the layer with a dose of.gtoreq. about 10.sup.15 ions/cm.sup.2 and a subsequent anneal at a temperature of.gtoreq. about 500.degree. C. for a predetermined time.

Method for forming a thin dielectric layer on a substrate

Disclosed is a thin dielectric inorganic layer overlaying a substrate, and having a thickness of .ltoreq. about 20 nm and a defect density of .ltoreq. about 0.6 defects/cm.sup.2 determined by BV measurements. Also disclosed is a method of forming such a layer, according to which a layer having the desired composition and thickness is formed on a substrate, followed by an ion implanatation into the substrate through the layer with a dose of .gtoreq. about 10.sup.15 ions/cm.sup.2 and a subsequence anneal at a temperature of .gtoreq. about 500.degree. C. for a predetermined time.

A method for fabricating a semiconductor integrated circuit structure having a submicrometer length device element is described wherein a surface isolation pattern is formed in a semiconductor substrate to define regions which are designated to contain devices. A first insulating compound layer is formed on the surface of the semiconductor substrate which is designated to be in part the gate dielectric. Subsequently, a polycrystalline silicon layer is deposited onto the compound layer. The polycrystalline silicon layer is heavily doped by phosphorus ion implantation and annealed below about 850.degree. C. Polycrystalline silicon portions are delineated by photolithography and dry etching. Dry etching is carried out in SF.sub.6 -Cl.sub.2 /He at a low power density of about 0.1 to 0.3 watts/cm.sup.2. The remaining portions of polycrystalline silicon layer are subjected to a thermal oxidation at a temperature of about 800.degree. C. during which controllable quantities of the polycrystalline silicon are consumed. After removal of the thermally grown oxide, polycrystalline silicon portions are obtained with length and thickness dimensions reduced by a desired amount. If polycrystalline silicon portions are to be reduced only in length, the horizontal surfaces of these portions are protected during oxidation by a cap. The cap may include a several nm thick silicon nitride layer which is arranged on a silicon dioxide stress-relieve layer. The method is particularly useful in forming a submicrometer length gate electrode of a field effect transistor.

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Boeblingen, Germany

Wolfgang Euen