International Business Machines Corporation

Wiren Dale Becker

Daniel Mark Dreps

Jose A Hejase

George A Katopis

William Louis Brodsky

Anand Haridass

Sungjun Chun

Milnes P David

Frank David Ferraiolo

Marc Henri Coq

Robert J Reese

Erich Klink

Glen Arthur Wiedemeier

Timothy Gerard McNamara

Roland Frech

Ryan Elsasser

Thomas-Michael Winkel

Syed F Hossain

Si T Win

John G Torok

Bruce John Chamberlin

Matteo Cocchini

Michael Cracraft

Michael F McAllister

Howard Harold Smith

Tingdong Zhou

Zhaoqing Chen

Allan Harvey Dansky

Charlie Chornglii Hwang

Peter J Camporese

Dale E Hoffman

Junyan Tang

Ching-Lung L Tong

Pavel Roy Paladhi

Kwok Fai Eng

Bhupindra Singh

Bjorn J Ahbel

Brian Samuel Beaman

Andreas Huber

Jinwoo Choi

Joshua C Myers

Dierk Kaller

Lawrence Alfred Clevenger

Evan G Colgan

Arvind Kumar

Xiao Hu Liu

Joshua M Rubin

Ruchir Puri

Steven Lorenz Wright

Edward Joseph Seminaro

Gary Franklin Goth

Sudipta Kumar Ray

Michael J Fisher

Nam Huu Pham

Haoxing Ren

Robert Anthony Rita

Hubert Harrer

Bao G Truong

Dinesh Gupta

Paul David Muench

Herbert I Stoller

Hua Xiang

Ethan E Cruz

Bradley David McCredie

Wai Mon Ma

Gerhard H Ruehle

Gerald J Fahr

Francesco Preda

James Patrick Eckhardt

Joseph P Corrado

Craig R Selinger

Kathleen M Wiley

Bernd Garben

Charles Kyriakos Vakirtzis

Alan Daniel Stigliani

Simone Rehm

Alan F Becker

Gerald W Mahoney

Andreas Rebmann

Helmut Virag

An enhanced integrated circuit interconnect package, method and multiple-layer integrated circuit laminate structure enable increased routing density per layer and maintains signal integrity performance. A differential signal via pair of vertical interconnect vias provide differential signaling. The vias of the differential signal via pair are positioned closely spaced together with each via offset from a center axis of an associated LGA contact, minimizing space between the differential signal vias and maintaining signal integrity performance, and providing increased available wiring signal channel.

Dense via pitch interconnect to increase wiring density

Methods and apparatuses for vertically transitioning signals between substrate integrated waveguides within a multilayered printed circuit board (PCB) are disclosed. A first substrate integrated waveguide (SIW) is provided in a first layer of the PCB, the first SIW having a first terminal portion. A second SIW is provided in a second layer of the PCB, the second SIW having a second terminal portion that overlaps with the first terminal portion, wherein a first ground plane separates the first SIW and the second SIW. A vertical transition comprising an aperture in the first ground plane that is disposed in an area defined by the overlap of the first terminal portion and the second terminal portion, such that a signal propagated in the first SIW transitions to the second SIW in a different layer through the aperture.

Vertically transitioning between substrate integrated waveguides (SIWs) within a multilayered printed circuit board (PCB)

A printed circuit board ('PCB') including a substrate integrated waveguide ('SIW') formed using two ground planes representing the top and bottom walls of the waveguide, tightly pitched ground vias to act as two side walls and two back walls, and a pair of monopole antennas placed at each end of the SIW acting as signal feeding/receiving structures is disclosed. The waveguide dominant mode cut off frequency is determined by the spacing between the two side walls. Within each monopole antenna pair, the first monopole antenna operates at a first frequency while the second monopole antenna operates at another frequency. For each monopole antenna pair, the first monopole antenna and the second monopole antenna are located in the SIW at a distance from the back wall optimal for each operating frequency.

PCB with substrate integrated waveguides using multi-band monopole antenna feeds for high speed communication

A multi-chip package structure includes a package substrate, an interconnect bridge device, first and second integrated circuit chips, and a connection structure. The first integrated circuit chip is flip-chip attached to at least the interconnect bridge device. The second integrated circuit chip is flip-chip attached to the interconnect bridge device and to the package substrate. The interconnect bridge device includes (i) wiring that is configured to provide chip-to-chip connections between the first and second integrated circuit chips and (ii) an embedded power distribution network that is configured to distribute at least one of a positive power supply voltage and a negative power supply voltage to at least one of the first and second integrated circuit chips attached to the interconnect bridge device. The connection structure (e.g., wire bond, injection molded solder, etc.) connects the embedded power distribution network to a power supply voltage contact of the package substrate.

Multi-chip package structure having high density chip interconnect bridge with embedded power distribution network

An assembly is provided including a flexible conduit and a device connectable to a generally central portion of the flexible conduit. The device includes a base. Movement of the base relative to an adjacent surface is restricted. At least one biasing assembly is attached to the base. The generally central portion of the flexible conduit is connected to the at least one biasing assembly. The at least one biasing assembly is configured to deform when a force is applied near a first end of the flexible conduit such that the force is not transmitted to a second end of the flexible conduit.

Slack and strain control mechanism

A heat sink structure is provided having fins mechanically altered dynamically to change and optimize the heat sink's performance based on certain environmental conditions. Specifically, the shape of fins of the heat sink structure is dynamically altered in response to environmental conditions that indicate the need for increased thermal performance by spreading the fins through a mechanical device dynamically, or by collapsing the fins to reduce pressure drop across a region when increased thermal performance is not needed.

Structural dynamic heat sink

Embodiments of the present invention include a method for fabricating a hybrid land grid array connector and the resulting structures. A body is provided. The body includes a first plurality of holes and a second plurality of holes. A conductive layer is deposited on the top and bottom surfaces of the body and the wall surfaces of the first plurality of holes resulting in the top and bottom surfaces being electrically common. The conductive layer is removed from the wall surfaces of a first subset of the first plurality of holes. A portion of the conductive layer is removed from the top surface of the body and the bottom surface of the body from an area surrounding the first subset of the first plurality of holes.

Method for fabricating a hybrid land grid array connector

Connector having a body with a conductive layer common to top and bottom surfaces of the body as well as to wall surfaces of a plurality of holes in the body

Embodiments of the present disclosure provide methods for using a compliance model to determine compatibility of a channel with a bus's chip I/O circuitry at its ends. The method includes identifying at least one design criteria and obtaining boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria. In certain embodiments, the boundary sets may be derived using a genetic algorithm. The method further includes verifying whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels.

Frequency-domain high-speed bus signal integrity compliance model

Embodiments of the present disclosure provide methods for testing channel compliance. The method generally includes identifying at least one design criteria and determining boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria. The boundary sets may be used for verifying whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels.

Embodiments of the present disclosure provide apparatus for testing channel compliance. The apparatus generally performs operations that includes identifying at least one design criteria and determining boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria. The boundary sets may be used for verifying whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels.

Structurally dynamic heat sink

Embodiments of the present disclosure provide apparatus for using a compliance model to determine compatibility of a channel with a bus's chip I/O circuitry at its ends. The apparatus includes at least one processor and a memory coupled to the at least one processor. The processor is configured to: identify at least one design criteria; obtain boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria; and verify whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels.

A dual in-line memory module (DIMM) connector system is provided. The DIMM connector system includes a motherboard, a DIMM card and a connector by which the DIMM card is coupled with the motherboard. The motherboard includes a printed circuit board (PCB) formed of a mid-loss dielectric constant material, signal pads that are thinner than ground pads, ground pads disposed proximate to signal pads, signal vias connected to distal edges of signal pads and shared antipads. The DIMM card includes a printed circuit board (PCB) formed of a mid-loss dielectric constant material, signal pads that are thinner than ground pads, signal vias connected to distal edges of signal pads and shared antipads for respective pairs of signal vias.

DIMM connector region vias and routing

Growing community of inventors

Hyde Park, NY, United States of America

Wiren Dale Becker