Adeia Semiconductor Bonding Technologies Inc.

Texas Instruments Corporation

Willmar E Subido

Wael Zohni

Ashok S Prabhu

Abiola A Awujoola

Zhuowen Sun

Edgardo R Hortaleza

Rajesh Katkar

Laura Wills Mirkarimi

Reynaldo Co

Wei-Yan Shih

Kyong-Mo Bang

Gabriel Z Guevara

Bongsub Lee

Howard Raeburn Test

Akash Agrawal

Tu Tam Vu

Xuan Li

Long Huynh

Stuart M Jacobsen

Gonzalo Amador

Kendall S Wills

Charles Anthony Odegard

Arthur M Wilson

Christopher Lattin

Ray D Harrison

Marjorie Cara

Jianbai Zhu

Hoang Nguyen

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

Wire bond wires for interference shielding

Apparatuses relating generally to a vertically integrated microelectronic package are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface. A first microelectronic device is coupled to the upper surface of the substrate. The first microelectronic device is a passive microelectronic device. First wire bond wires are coupled to and extend away from the upper surface of the substrate. Second wire bond wires are coupled to and extend away from an upper surface of the first microelectronic device. The second wire bond wires are shorter than the first wire bond wires. A second microelectronic device is coupled to upper ends of the first wire bond wires and the second wire bond wires. The second microelectronic device is located above the first microelectronic device and at least partially overlaps the first microelectronic device.

Embedded wire bond wires

An apparatus relates generally to a microelectronic package. In such an apparatus, a microelectronic die has a first surface, a second surface opposite the first surface, and a sidewall surface between the first and second surfaces. A plurality of wire bond wires with proximal ends thereof are coupled to either the first surface or the second surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from either the first surface or the second surface, respectively, of the microelectronic die. A portion of the plurality of wire bond wires extends outside a perimeter of the microelectronic die into a fan-out ('FO') region. A molding material covers the first surface, the sidewall surface, and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material.

Wafer-level packaging using wire bond wires in place of a redistribution layer

An apparatus, and methods therefor, relates generally to an integrated circuit package. In such an apparatus, a platform substrate has a copper pad. An integrated circuit die is coupled to the platform substrate. A wire bond wire couples a contact of the integrated circuit die and the copper pad. A first end of the wire bond wire is ball bonded with a ball bond for direct contact with an upper surface of the copper pad. A second end of the wire bond wire is stitch bonded with a stitch bond to the contact.

Ball bonding metal wire bond wires to metal pads

An apparatus relates generally to a microelectromechanical system component. In such an apparatus, the microelectromechanical system component has a lower surface, an upper surface, first side surfaces, and second side surfaces. Surface area of the first side surfaces is greater than surface area of the second side surfaces. The microelectromechanical system component has a plurality of wire bond wires attached to and extending away from a first side surface of the first side surfaces. The wire bond wires are self-supporting and cantilevered with respect to the first side surface of the first side surfaces.

Coupling of side surface contacts to a circuit platform

The invention provides methods and systems for laser assisted wirebonding. One or more conditioning laser pulses are used to prepare a bonding surface for wirebonding by removing impurities such as residues from manufacturing processes, oxides, or irregularities on the bonding surface. Subsequently, a free air ball is brought into contact with the conditioned bonding surface to form a weld.

Methods and systems for laser assisted wirebonding

A semiconductor assembly comprising an integrated circuit chip with a first plurality of metallic contact pads exposed, having a pitch center-to-center of less than 180 &#x3bc;m. A metallic bump of reflowable metal is attached to each of these contact pads. The assembly further has an electrically insulating substrate with a second plurality of metallic terminal pads in locations matching the locations of the contact pads. Each of the bumps also attached to these matching terminal pads, respectively, whereby the chip is interconnected with the substrate spaced apart by a gap. An adherent polymeric encapsulant fills the gap so that the encapsulant is free of voids. It is a pivotal feature in the method that vibration energy, up to ultrasonic frequencies, is used while the encapsulant is still in a low-viscosity precursor state in order to ensure the void-free spreading of the precursor throughout the gap between chip and substrate. The vibration energy ensures uniform underfill distribution even when the gap and the bump pitch are narrow, with uniform distribution of any fillers, and enhanced adhesion to chip, substrate and bumps.

Vibration-assisted method for underfilling flip-chip electronic devices

Wire bonding process for copper-metallized integrated circuits

The present invention provides a system and method for preparing semiconductor integrated circuits (&ldquo;ICs&rdquo;), particularly ball grid arrays (&ldquo;BGAs&rdquo;), quad flat packs (&ldquo;QFPs&rdquo;) and dual in line packages (&ldquo;DIPs&rdquo;) for failure analysis (&ldquo;FA&rdquo;) using a variety of techniques, including emission microscopy (&ldquo;EM&rdquo;) and externally induced voltage alteration (&ldquo;XIVA&rdquo;). This system and method requires precision thinning and polishing of the semiconductor IC device to expose the backside of the die and mounting of the semiconductor device on a secondary package assembly.

Repackaging semiconductor IC devices for failure analysis

Growing community of inventors

Garland, TX, United States of America

Willmar E Subido