Fujitsu Corporation

William T Chou

Solomon I Beilin

Wen-chou Vincent Wang

Michael G Lee

Michael G Peters

James J Roman

Larry Louis Moresco

David Kudzuma

David A Horine

Som S Swamy

Tetsuzo Yoshimura

Thomas Joel Massingill

Teruo Murase

Masaaki Inao

Yashuhito Takahashi

Yasuhito Takahashi

David G Love

Connie M Wong

Richard L Wheeler

David Dung Ngo

Lei Zhang

Opto-electrical systems having electrical and optical interconnections formed in thin layers are disclosed. In one set of preferred embodiments, optical signals are conveyed between layers by respective vertical optical couplers disposed on the layers. In other preferred embodiments, optical signals are conveyed by stack optical waveguide coupling means. Yet other preferred embodiments have electrical via means formed in one or more layers to covey electrical signals between two or more layers.

Multi-layer opto-electronic substrates with electrical and optical interconnections and methods for making

Methods of planarizing structures formed on the surfaces of substrates and wafers are disclosed. The methods form a planarizing layer over the surface and the structures, or the locations where the structures are to be formed, such that the top surface of the layer has low areas between the locations of the structures, and such that the low areas lie substantially within a plane which is below the tops of the structures. A polish-stop layer is thee formed over the low areas of the planarizing layer, the polish-stop layer being more resistant to polishing than the planarizing layer and, preferably, the structures. The resulting surface is then polished. The polishing may be accomplished by, for example, standard mechanical polishing, and chemical-mechanical polishing.

Methods of planarizing structures on wafers and substrates by polishing

Three-dimensional opto-electronic modules having a plurality of opto-electronic (O/E) layers, with optical signals being routed between O/E layers within one or more three-dimensional volumes, are disclosed. In preferred embodiments, the O/E layers are disposed over and above one another with at least one of their edges aligned to one another. At least two of the O/E layers have waveguides with ends near the aligned edges. A plurality of Zconnector arrays are disposed between the O/E layers and within the three-dimensional volumes to provide a plurality of Zdirection waveguides. A first vertical optical coupler couples light from one waveguide in one O/E layer to a Z-direction waveguide, and a second vertical optical coupler couples the light from the Z-direction waveguide to a second waveguide in a second O/E layer. In further preferred embodiments, segments of the Z-connector arrays are held by a holding unit.

Three-dimensional opto-electronic modules with electrical and optical interconnections and methods for making

A method of fabricating a multilayer interconnected substrate is disclosed. In one embodiment, the method includes providing a structure having a dielectric substrate having a first substantially planar surface and an opposing second substantially planar surface. A first conductive layer is disposed on the first substantially planar surface of the dielectric substrate, and an interface is present between the first conductive layer and the dielectric substrate. A blind via site is formed in the structure, and through the dielectric substrate to the interface between the first conductive layer and the dielectric substrate. The blind via site is filled with a conductive material by an electrolytic plating process.

Method of fabricating a substrate with a via connection

Disclosed is device and/or material integration into thin opto-electronic layers, which increase room for chip-mounting, and reduce the total system cost by eliminating the difficulty of optical alignment between opto-electronic devices and optical waveguides. Opto-electronic devices are integrated with optical waveguides in ultra thin polymer layers on the order of 1 &mgr;m to 250 &mgr;m in thickness.

Opto-electronic substrates with electrical and optical interconnections and methods for making

Opto-electrical systems having electrical and optical interconnections formed in thin layers with thin-film active devices are disclosed. In one embodiment, optical connections are made between the edge of one substrate and the surface of another substrate with the use of photorefractive materials. In another embodiment, the optical connection is made by separating a optical film from the first substrate and coupling the first substrate and the optical film to separate receptacles located on the second substrate. Film optical link modules employing aspects of the invention are also disclosed.

Systems based on opto-electronic substrates with electrical and optical interconnections and methods for making

An interposer for providing power, ground, and signal connections between an integrated circuit chip or chips and a substrate. The inventive interposer includes a signal core and external power/ground connection wrap. The two sections may be fabricated and tested separately, then joined together using z-connection technology. The signal core is formed from a conductive power/ground plane positioned between two dielectric layers. A patterned metal layer is formed on each dielectric layer. The two metal layers are interconnected by a through via or post process. The conductive power/ground plane functions to reduce signal cross-talk between signal lines formed on the two patterned metal layers. The power/ground wrap includes an upper substrate positioned above the signal core and a lower substrate positioned below the signal core. The upper and lower substrates of the power/ground wrap are formed from a dielectric film having a patterned metal layer on both sides, with the patterned layers connected by a through via or post process. The two power/ground wrap substrates may be formed separately or from one substrate which is bent into a desired form (e.g., a &ldquo;U&rdquo; shape). The two power/ground substrates are maintained in their proper alignment relative to the signal core and to each other by edge connectors which are also connected to the signal core's intermediary power/ground plane.

Reduced cross-talk noise high density signal interposer with power and ground wrap

Several inventive features for increasing the yield of substrate capacitors are disclosed. The inventive features relating to selective placement of insulating layers and patches around selected areas of the capacitor's main dielectric layer. These insulating layers and defects prevent certain manufacturing processing steps from creating pin-hole defects in the main dielectric layer. The inventive features are suitable for any type of material for the main dielectric layer, and are particularly suited to anodized dielectric layers.

Power conducting substrates with high-yield integrated substrate capacitor

Methods of etching polyamic acid layers and the like are disclosed. In exemplary embodiments of the present invention, the polymeric acid layer to be etched is alternatively exposed to etchant solutions (etchants) and rinse solutions, where the etchant solutions are of relatively moderate alkalinity and the rinse solutions have a lower pH than the etchant solutions. The present invention enables polymeric acid layers to be developed with standard basic etchants at relatively moderate concentrations and at room temperature with little, if any, corrosion to any underlying metal layers. The present invention enables the more reliable and cleaner spin-spray processing method to be employed, thereby significantly increasing yields and reducing overall processing costs. The present invention also enables the etching of thick layers of polymeric acid without the need for special treatments, such as exposure to highly concentrated etchant solutions or high temperature processing conditions.

Method of patterning polyamic acid layers

A method for plating conductive material in through apertures and blind apertures of a substrate which has a conductive material on its upper and lower surfaces. In a typical configuration for plating a via, there is a first region of conductive material adjacent to, but outside of, the aperture which forms the via and a second region of conductive material inside of the aperture. The second conductive region is selected to be the cathode of the plating process. The structure is placed in a plating bath, a first potential is applied to the first region of conductive material, and a second potential is applied to the second region of conductive material, with the second potential being different from the first potential. Under these conditions, material will plate onto the second region of conductive material to fill the aperture. The value of the first potential is preferably selected to substantially reduce the rate at which the first region of conductive material is etched by the plating bath, and may be used to cause material to be plated onto first region, but at a slower rate than the plating of the second conductive region.

Method for electroplating vias or through holes in substrates having conductors on both sides

A method of fabricating a multi-layer interconnected substrate structure. The inventive method includes forming a multi-layer structure from multiple, pre-fabricated power and/or signal substrates which are laminated together. A drill is then used to form a via through the surface of a ring-type pad down to a desired depth in the multi-layer structure. The via hole is cleaned and then filled with a conductive material. The via so formed between two or more substrates is self-aligned by using the ring pad(s). This contributes to an increased signal routing density compared to conventional methods.

Method of fabrication of multiple-layer high density substrate

An interposer substrate for mounting an integrated circuit chip to a substrate, and method of making the same, are shown. The interposer substrate comprises power supply paths and controlled impedance signal paths that are substantially isolated from each other. Power supply is routed through rigid segments and signals are routed through a thin film flexible connector that runs from the upper surface of the interposer substrate to the lower surface. Bypass capacitance is incorporated into the interposer substrate and connected to the power supply so that it is positioned very close to the integrated circuit chip. The interposer may be fabricated by forming a multilayered thin film structure including the signal paths over a rigid substrate having vias formed therein, removing the central portion of the substrate leaving the two end segments, and folding and joining the end segments such that the vias are connected. In another embodiment of the invention, a separate power plate is provided for carrying the power lines. Portions of the power plate, with a multilayered thin film structure thereon, are cut and folded to form interposers. Methods of making single-chip interposers are also disclosed.

Controlled impedance interposer substrate and method of making

An interposer for providing power, ground, and signal connections between an integrated circuit chip or chips and a substrate. The interposer includes a signal core and external power/ground connection wrap. The two sections may be fabricated and tested separately, then joined together using z-connection technology. The signal core is a dielectric film with patterned metal on both sides. The two metal layers are interconnected by a through via or post process. The power/ground wrap includes an upper substrate positioned above the signal core and a lower substrate positioned below the signal core. The upper and lower substrates of the power/ground wrap are formed from a dielectric film having a patterned metal layer on both sides connected by a through via or post process. The upper power/ground wrap substrate, signal core, and lower power/ground substrate are interconnected as desired using z-connection technology (e.g., solder or conductive ink). The power/ground layers on the upper substrate can be connected to the power/ground layers on the lower substrate by suitable edge connectors. With an integrated circuit chip or chips connected to the upper layer of the top substrate of the power/ground wrap and a printed circuit board or other mounting substrate connected to the bottom layer of the lower substrate of the wrap, the inventive interposer provides a set of high density and electrically isolated signal, power, and ground interconnections.

High density signal interposer with power and ground wrap

Processes for forming conductive vias between circuit elements formed on either side of a flexible substrate are disclosed. In one embodiment, the inventive process starts with a flexible film polyimide substrate on each side of which is arranged a layer of copper. Both of the copper surfaces are coated with photoresist. Blind vias are then drilled through the top copper layer and substrate using a laser. The photoresist is then exposed (patterned). A plating operation is used to fill the vias with a conductive material. The resist is then developed and the line and pad structures on the surface of the copper layer are plated. The photoresist is then stripped. In a variation of this embodiment, the photoresist is imaged prior to drilling of the vias using a laser. In an alternative embodiment of the inventive process, a through hole is drilled instead of a blind via. In either embodiment, there is no process step between the photo-exposure of the resist and the laser drilling which can impact the dimensions of the substrate.

Process flows for formation of fine structure layer pairs on flexible

Methods of forming patterns in photo-sensitive resist layers with high aspect ratio features are described. The photosensitive layer is patterned exposed to actinic radiation and thereafter developed. For high aspect ratio patterns, the inventors have often observed a residue of resist material at the bottom of such features, and that this residue interferes with subsequent processing, such as filling the pattern with metal by a plating operation. To remove this residue, the patterned locations of the resist are exposed to a low dose of low-energy electron beam radiation, preferably having energy of less than 6 KeV and dosage of less than 200 .mu.C/cm.sup.2. After the electron beam exposure, the aperture is again exposed to a developer solution, which may be of the same composition as the developer initially used to develop the patterns.

Growing community of inventors

Cupertino, CA, United States of America

William T Chou