International Business Machines Corporation

Advanced Semiconductor Engineering, Inc.

Agency for Science, Technology and Research

Other

Sematech, Inc.

Institute of Materials Research and Engineering

William T Chen

Chih-Pin Hung

Chen-Chao Wang

Ajit Kumar Trivedi

Chi Shih Chang

John Richard Hunt

John Ulrich Knickerbocker

Wayne John Howell

Joseph Angelo Benenati

Claude Louis Bertin

William R Tonti

Mark Vincent Pierson

Wayne Frederick Ellis

James Robert Wilcox

Jerzy Maria Zalesinski

Thomas P Gall

Peter Malcolm Moran

Thomas E Dinan

Tien Y Wu

Mark David Poliks

Natalie Barbara Feilchenfeld

Bernd Karl Appelt

Yuan-Chang Su

Anthony P Ingraham

Chih-Yi Huang

Shih-Fu Huang

Francis Charles Burns

Lisa A Fanti

Chia-Cheng Chen

Lawrence Robert Blumberg

Douglas H Strope

Yifan Guo

Gary R Carden

Stanley M Albrechta

Eugene P Skarvinko

John J Kaufman

Ta-Chun Lee

George Dean Ogden

Andrew R Gresko

Nadia Tonsi

Calvin Cheung

Harvey M Phillips

Syamal Kumar Lahiri

A semiconductor device package includes: a redistribution stack including a dielectric layer defining a first opening; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending from the first portion of the first trace, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, the first opening in the dielectric layer has a maximum width along the first transverse direction, and the maximum width of the second portion of the first trace is less than the maximum width of the first opening.

Semiconductor device packages and stacked package assemblies including high density interconnections

A semiconductor device package comprises a bottom electronic device, an interposer module, a top electronic device, and a double sided redistribution layer (RDL) structure. The interposer module includes a plurality of conductive vias. The top electronic device has an active surface and is disposed above the bottom electronic device and above the interposer module. The double sided RDL structure is disposed between the bottom electronic device and the top electronic device. The active surface of the bottom electronic device faces toward the double sided RDL structure. The active surface of the top electronic device faces toward the double sided RDL structure. The double sided RDL structure electrically connects the active surface of the bottom electronic device to the active surface of the top electronic device. The double sided RDL structure electrically connects the active surface of the top electronic device to the interposer module.

Stacked semiconductor package assemblies including double sided redistribution layers

A method of forming a semiconductor device package includes: (1) providing an electronic device including an active surface and a contact pad adjacent to the active surface; (2) forming a package body encapsulating portions of the electronic device; and (3) forming a redistribution stack, including: forming a dielectric layer over a front surface of the package body, the dielectric layer defining a first opening exposing at least a portion of the contact pad; and forming a redistribution layer (RDL) over the dielectric layer, the RDL including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, and the maximum width of the second portion of the first trace is no greater than 3 times of a width of the first portion of the first trace, wherein the second portion of the first trace is disposed between and spaced from opposing sidewalls of the dielectric layer defining the first opening.

A semiconductor device package includes: (1) an electronic device including an active surface and a contact pad adjacent to the active surface; and (2) a redistribution stack including a dielectric layer disposed over the active surface and defining a first opening exposing at least a portion of the contact pad; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, and the maximum width of the second portion of the first trace is no greater than 3 times of a width of the first portion of the first trace, wherein the second portion of the first trace is disposed between and spaced from opposing sidewalls of the dielectric layer defining the first opening.

A semiconductor device package includes an electronic device and a redistribution stack. The redistribution stack includes a dielectric layer disposed over an active surface of the electronic device and defining an opening exposing at least a portion of a contact pad of the electronic device. The redistribution stack also includes a redistribution layer disposed over the dielectric layer and including a trace. A first portion of the trace extends over the dielectric layer along a longitudinal direction adjacent to the opening, and a second portion of the trace is disposed in the opening and extends between the first portion of the trace and the exposed portion of the contact pad. The second portion of the trace has a maximum width along a transverse direction orthogonal to the longitudinal direction, and the maximum width of the second portion of the trace is no greater than about 3 times of a width of the first portion of the trace.

A substrate having single patterned metal layer includes a patterned base having at least a plurality of apertures, the patterned metal layer disposed on the patterned base, and a first surface finish layer. Parts of the lower surface of the patterned metal layer are exposed by the apertures of the patterned base to form a plurality of first contact pads for downward electrical connection externally, and parts of the upper surface of the patterned metal layer function as a plurality of second contact pads for upward electrical connection externally. The first surface finish layer is disposed at least on one or more surfaces of the second contact pads, and the first surface finish layer is wider than the second contact pad beneath. A package applied with the substrate disclosed herein further comprises at least a die conductively connected to the second contact pads of the substrate.

Substrate having single patterned metal layer, and package applied with the substrate , and methods of manufacturing of the substrate and package

The present invention discloses techniques that improve the reliability of a flip packages that uses underfill encapsulation. One embodiment of the present invention describes a method and apparatus of packaging a flip chip by relocating the neutral plane of the package substrate away from its mid-plane. Another embodiment of the present invention describes a method and apparatus of arranging the layers of a laminate for use in PBGA packaging that arranges the layers of the laminate according to the stiffness of each layer. Another embodiment of the present invention describes a method and apparatus of packaging a flip chip that uses one or more redundant interconnections at the bottom of the package substrate where the redundant interconnections are within the shadow of the IC chip.

Placement of sacrificial solder balls underneath the PBGA substrate

A method of forming a metallic feature on a substrate, comprising the steps of: providing a stamp having a raised region; depositing catalytic particles on a selected area of the stamp, including the raised region thereof; providing a substrate; applying the stamp to the substrate, such that the raised region of the stamp causes a corresponding indented region in the substrate and at least some of the catalytic particles are transferred to a selected area of the substrate; and plating the selected area of the substrate.

Method and apparatus for forming a metallic feature on a substrate

A method of plating an aromatic polymer substrate comprises: applying a strippable coating of a non-aromatic polymer to a substrate surface to be plated; selectively illuminating the coated substrate surface with laser light to ablate a selected area of the strippable coating and to activate an underlying region of the substrate surface exposed by the ablation of the strippable coating; contacting the substrate surface with a seeding solution containing polymer-stabilised catalytic seeding particles, so that the seeding particles adhere preferentially to the activated region of the substrate; and electrolessly plating the substrate surface, whereby the seeded areas of the substrate surface are selectively plated.

Method of forming selective electroless plating on polymer surfaces

An integrated circuit assembly has pads of a chip electrically connected to pads of a substrate with rolling metal balls. A pliable material bonds the balls in movable contact with pads of the chip and substrate. Because the balls are relatively free to move, thermal expansion differences that would ordinarily cause enormous stresses in the attached joints of the prior art, simply cause rolling of the balls of the present invention, avoiding thermal stress altogether. Reliability of the connections is substantially improved as compared with C4 solder bumps, and chips can be safely directly mounted to such substrates as PC boards, despite substantial thermal mismatch.

Rolling ball connector

The present invention describes a method and apparatus for packaging a flip chip by matching the z-direction CTE of the IC solder joint with the z-direction CTE of the encapsulant. Consideration of the z-direction CTE's is important when determining the volumetric CTE of the encapsulant. This invention first requires a determination of the z-direction CTE of the IC solder joint and a determination of the z-direction CTE of the encapsulant. The invention next matches the z-direction CTE of the IC solder joint to the z-direction CTE of the encapsulant. The matching of the two z-direction CTE's reduces the z-direction tensile or compression stresses on the IC solder joint and the encapsulant.

Proper choice of the encapsulant volumetric CTE for different PGBA substrates

An apparatus for and method of minimizing the thermo-mechanical fatigue of flip-chip packages. The interposer of the present invention, preferably comprising an organic polymer such as polyimide, contains apertures having conductive plugs inserted therein for joining a chip to a substrate in an electronic module utilizing flip-chip packaging. The interposer is selected to provide optimum spacing between the chip and substrate having a coefficient of thermal expansion adapted to the thermal cycling temperature extremes of the module components. The interposer may comprise an inner core with two adhesive outer layers which may comprise different materials to promote adhesion at their respective interfaces within a module. Conductive plugs are disposed within the apertures of the interposer comprising of a first and second solder or comprising a conductive plug having top and bottom surfaces coated with a conductive adhesive. Preferably, the first solder is disposed within an interior of the apertures and the second solder is disposed within an exterior of the apertures such that the first solder is between a first portion and a second portion of the second solder. Upon reflow, the second solder is reflowed while the first solder remains solid.

Underfill preform interposer for joining chip to substrate

Relocating the neutral plane in a PBGA substrate to eliminate chip crack and interfacial delamination

An area array flip chip device produced using wire bonding technology. The design and process for producing such a flip chip involves stud bumps which are bonded on the substrate, to give good electrical interconnections between the chip pads and the substrate pads. This completely eliminates the limitation of not being able to have stud bump interconnections over the active area of the chip, and allows the stud bump interconnection method to be applied over the entire chip area. The design and process can also be applied to the joining of a substrate or first level packaging to the board. In this embodiment, the stud bump process acts as a replacement for the BGA process.

Area array stud bump flip chip device and assembly process

Growing community of inventors

Endicott, NY, United States of America

William T Chen