International Business Machines Corporation

William Stanford Johnson

Ronald W Knepper

David DeWitt

Kenneth Howard Christie

A method for fabricating an N-channel silicon MOS field effect transistor on a P-type substrate. The structure retains the natural isolation between devices and the consequent higher device density in an integrated circuit structure than conventional double diffused MOS field effect transistor devices. The device is fabricated by using ion implantation to create an N-type surface layer in the channel and then overcompensating this layer to create a P-type region near the source by ion implanting P-type ions into the source junction region. The source to substrate capacitance is considerably less than that of conventional double diffused MOS devices which provides an improved circuit performance.

Narrow channel length MOS field effect transistor with field protection

Method for forming a narrow channel length MOS field effect transistor

A metal nitride oxide semiconductor device capable of use within a memory cell, having a more heavily doped region of the same type as the substrate provided directly under the channel of the depletion mode device. Application of a positive write voltage to the gate of the device, with the substrate at 0 volts potential and the source and drain biased to a suitable positive level, results in avalanche operation of the device whereby charge is stored in a nitride oxide interface under the gate, thereby converting the device to enhancement mode operation. The charge can be removed with the source and drain biased to the 0 volt potential of the substrate and a positive erase signal applied to the gate. A four device memory cell is disclosed.

Non-volatile metal nitride oxide semiconductor device

The invention is concerned with methods for producing improved semiconductor devices. The invention is advantageously employable in the fabrication of insulated-gate field-effect transistor devices. The problem of accurately aligning the gate electrode over the channel region, lying between the source region and the drain region of a field effect transistor, is particularly addressed and solved. Accurate and precise field protection of all areas of the field-effect transistor surrounding the channel, source and drain regions is simply and effectively accomplished. The proper alignment of the gate electrode is largely accomplished by utilizing essentially the same mask structure to define the gate, source and drain regions. The same mask structure is utilized to define the area that is field protected.

Semiconductor devices

An integrated circuit structure with full dielectric isolation, i.e., the electrical isolation is provided by electrically insulative material, is formed by ion bombarding a silicon substrate with ions such as nitrogen, oxygen or carbon to implant subsurface region containing such ions and heating the resulted bombarded substrate to a temperature sufficient to react the introduced ions with the substrate to form a subsurface layer which has a different etchability than silicon. An epitaxial layer of monocrystalline silicon is then deposited on the substrate, after which a pattern of regions of electrically insulating material is formed extending through the epitaxial layer beyond the substrate surface into contact with the subsurface layer to laterally surround a plurality of pockets in said silicon. An electrically insulative layer is formed on the surface of the epitaxial layer continuous with the electrically insulating lateral regions. The silicon substrate below the subsurface layer is removed by etching in a solvent in which silicon is more etchable than is the subsurface layer to expose the subsurface layer, and the subsurface layer is etched away with a solvent in which this layer is more etchable than are the lateral regions of electrically insulating material. As a result, the planar surfaces of the silicon pockets are exposed, and selective conductivity-determining impurities may be introduced into the silicon pockets to form the devices of the integrated circuit.

Method for fabricating integrated circuit structures with full

A field effect transistor with spaced source and drain regions of a first type conductivity in a monocrystalline semiconductor body having a background impurity of a second opposite type conductivity, the improvement being a buried layer of a second type conductivity impurity having an average concentration higher than the impurity concentration of the background impurity that is located just beneath the insulating layer in the field regions of the device and at a greater depth in the gate region, the depth in the gate region being approximately equal to the thickness of the field insulating layer less the thickness of the gate insulating layer.

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Hopewell Junction, NY, United States of America

William Stanford Johnson