Advanced Micro Devices Corporation

Spansion Llc.

Advanced Micro Services

William S Brennan

Fred N Hause

H Jim Fulford

Robert Louis Dawson

Mark W Michael

Basab Bandyopadhyay

Paul Raymond Besser

Frederick N Hause

Errol Todd Ryan

John A Iacoponi

Peter J Beckage

Frank Mauersberger

Allen Lewis Evans

Tim Z Hossain

Joseph William Wiseman

Bryon K Hance

Brian D White

Minh Van Ngo

Charles E May

Lu You

Alexander H Nickel

Minh Quoc Tran

Hieu T Pham

Allen White

Pei-Yuan Gao

Don A Tiffin

Erik Wilson

Howard Ernest Castle

Amiya R Ghatak-Roy

Sung Jin Kim

David Soza

Berta Valdez

Renee S Prusik

Ian G Brown

Willie Rivera

Patrick L Smith

Devices and systems for insulating integrated circuits from ultraviolet ('UV') light are described. The device includes a conductive feature, a first and second UV blocking layer, a first and second insulating laver, and a conductive structure. The first insulating layer overlays the first UV blocking layer. A via opening extends through the first insulating layer and the first UV blocking layer. The second UV blocking layer overlays the first insulating laver. The second insulating layer overlays the second UV blocking layer. An interconnect trench is defined in the second insulating layer and second UV blocking layer. The conductive structure is electrically connected to the conductive feature and extends into the via opening and along the interconnect trench.

Electronic devices with ultraviolet blocking layers

A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% Nwith less than 10% H, performing planarization, performing in-situ low-H NHplasma treatment and low Si&#x2014;H SiN etch stop layer deposition, and performing remaining back end processing.

[object Object]

A process of forming an electronic device including forming a first ultraviolet ('UV') blocking layer over a conductive feature, wherein the first UV blocking layer lies within 90 nm of the conductive structure; forming a first insulating layer over the first UV blocking layer; and patterning the first insulating layer and the first UV blocking layer to form a first opening extending to the conductive feature, wherein during the process, the first UV blocking layer is exposed to UV radiation.

Method of forming an electronic device

A technique for use in fabricating an integrated circuit are disclosed. The method generally begins by performing an operation on a wafer using a fabrication tool. Next, volatiles are desorbed from the wafer. The desorbed volatiles are sampled and raw spectral data indicating the content of the desorbed volatiles is generated. The raw spectral data is subjected to a spectroscopic analysis. An operational parameter of the fabrication tool is then modified responsive to the result of the results of the spectroscopic analysis. In one particular aspect of the invention, a controller receives the raw spectral data and processes the raw spectral data to determine the presence of a residual material on the wafer. The controller then controls the process flow operation to reduce the amount of the residual material on the wafer responsive to the results of processing the raw spectral data. Other aspects of the invention include the apparatus implementing the process flow and the controller itself.

Closed loop residual gas analyzer process control technique

In another aspect of the present invention, a system for detecting an endpoint in a polishing process is provided. The system comprises a polishing tool, a controllable light source, a sensor, and a controller. The polishing tool is capable of polishing a surface of a semiconductor device, wherein the semiconductor device includes a first layer comprised of a first material and a second layer comprised of a second material. The first layer is positioned above the second layer. The controllable light source is capable of delivering light having one of a plurality of a preselected frequencies to the surface of the semiconductor device. The sensor is capable of detecting the light reflected from the surface of the semiconductor device. The controller is capable of determining the second material, instructing the controllable light source to deliver light of one of the frequencies in response to the second material, comparing the reflected light to a preselected setpoint, and modifying the polishing process in response to the reflected light exceeding the preselected setpoint.

Method and apparatus for detecting the endpoint of a chemical-mechanical polishing operation using optical techniques

The present invention is generally directed to various methods of controlling copper barrier/seed deposition processes, and a system for accomplishing same. In one illustrative embodiment, the method comprises performing at least one process operation to form a barrier metal layer and a copper seed layer above a wafer, sensing at least one parameter of at least one process operation and determining an acceptability metric for the barrier metal layer and the copper seed layer based upon the sensed at least one parameter. In some embodiments, the method further comprises modifying at least one parameter of said at least one process operation to be performed to form a barrier metal layer and a copper seed layer on a subsequently processed wafer based upon said determined acceptability metric. In some embodiments, the method further comprises identifying a wafer as unacceptable if said acceptability metric falls below a preselected level. In some embodiments, the acceptability metric may be determined by accessing a model that correlates the sensed parameter(s) to an acceptability metric for the barrier metal layer and the copper seed layer. In one embodiment, the system is comprised of a process tool that is adapted to perform at least one process operation, e.g., an etch process, a degas process, a barrier metal deposition process and/or a copper seed deposition process, to form a barrier metal layer and a copper seed layer. The system further comprises a controller that is adapted to access a model to determine an acceptability metric for the barrier metal layer and copper seed layer based upon at least one sensed process parameter for at least one of the process operations performed in forming the barrier metal layer and copper seed layer.

Method and apparatus for controlling copper barrier/seed deposition processes

The present invention is generally directed to a transistor having a gate stack comprised of a metal, and a method of making same. In one illustrative embodiment, the transistor is comprised of a gate stack comprised of a gate insulation layer positioned above a semiconducting substrate, a layer of silicon positioned above the gate insulation layer, a layer of adhesion material positioned above the layer of silicon, a layer of metal positioned above the layer of adhesion material, and a plurality of source/drain regions formed in the substrate adjacent the gate stack.

Transistor having a gate stick comprised of a metal, and a method of making same

A method for forming a conductive interconnect comprises forming a process layer over a structure layer and forming a mask over the process layer, the mask having an etch profile therein. An anisotropic etching process is performed to erode the mask and to form an etched region in the process layer, the etched region having a profile correlating to the etch profile. A conductive material is formed in the etched region in the process layer and any excess conductive material is removed from above an upper surface of the process layer.

Method for forming openings for conductive interconnects

A test structure useful in controlling a polishing process of a semiconductor device is provided. The test structure is comprised of a structure layer, a first process layer, and interconnects. The first process layer is positioned above the structure layer and has a plurality of openings formed therein and extending at least partially therethrough to a preselected depth. At least a portion of the plurality of openings have a tapered region progressively narrowing in a direction from the first process layer toward the structure layer. The openings are spaced a preselected distance X apart. The interconnects are formed in the plurality of openings including the tapered region. Thus, as the process layer and interconnects are removed by the polishing process, the distance X increases, indicating the depth of the polishing process.

Test structure for providing depth of polish feedback

A method for forming a semiconductor having improved copper interconnects is provided. The method comprises forming a first dielectric layer above a first structure layer. Thereafter, a first opening is formed in the first dielectric layer, and a first copper layer is formed above the first dielectric layer and in the first opening. A portion of the first copper layer outside of the opening is removed. A surface portion of the first copper layer is also removed from within the opening, and a second layer of copper is formed above the first layer of copper, replacing the removed surface portion.

Method for forming copper interconnects

A method of forming conductive contacts or an integrated circuit device is disclosed herein. In one embodiment, the method comprises forming a transistor above a semiconducting substrate, and forming a first layer comprised of an orthosilicate glass material above the transistor and the substrate. The method further comprises forming a second layer comprised of an insulating material above the first layer, and performing at least one etching process to define an opening in the second layer for a conductive contact to be formed therein, wherein the first layer comprised of an orthosilicate glass material acts as an etch stop layer during the etching of the opening in the second layer.

Contact each methodology and integration scheme

Methods of removing gaseous phase contaminants from a processing chamber, such as a PVD chamber, are provided. In one aspect, a method of removing gaseous phase water from a processing chamber is provided that includes placing a heated substrate that has a titanium film in the processing chamber to dissociate a first portion of the gaseous phase water into hydrogen and oxygen and capture some of the oxygen in, the titanium film. The dissociated hydrogen and uncaptured oxygen are pumped from the processing chamber and the substrate is removed from the processing chamber. Pump down times and test wafer consumption may be reduced.

Method of improving vacuum quality in semiconductor processing chambers

A dielectric material is provided having air gaps purposely formed within the dielectric. The dielectric is deposited, and air gaps formed, between respective interconnect lines. The geometries between interconnect lines is purposely controlled to achieve a large aspect ratio necessary to produce air gaps during CVD of the dielectric. Air gaps exist between interconnects to reduce the line-to-line capacitance, and thereby reduce the propagation delay associated with closely spaced interconnects.

Dielectric having an air gap formed between closely spaced interconnect lines

An isolation technique is provided for improving the overall planarity of isolation regions relative to adjacent active area silicon mesas. The isolation process results in a trench formed in field regions immediately adjacent the active regions. The trench, however, does not extend entirely across the field region. By preventing large area trenches, substantial dielectric fill material and the problems of subsequent planarization of that fill material is avoided. Accordingly, the present isolation technique does not require conventional fill dielectric normally associated with a shallow trench process. While it achieves the advantages of forming silicon mesas, the present process avoids having to rework dielectric surfaces in large area field regions using conventional sacrificial etchback, block masking and chemical-mechanical polishing. The improved isolation technique hereof utilizes trenches of minimal width etched into the silicon substrate at the periphery of field regions, leaving a field mesa. A field dielectric, preferably oxide, is formed upon the field mesa and fills trenches between the field mesa and active mesas, leaving a substantially planar field dielectric commensurate with the upper surface of adjacent active mesas.

Semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization

A method for forming a multilevel interconnect structure having a globally planarized upper surface. Dielectrics are deposited upon a semiconductor to minimize pre-existing disparities in topographical height and to create an upper surface topography having a polish rate greater than that of lower regions. Subsequent chemical mechanical polishing produces a substantially planar surface.

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Austin, TX, United States of America

William S Brennan