Harris Corporation

William R Morcom

Hugh C Nicolay

Thomas J Sanders

Eugene R Cox

Jacob A Davis

Jeffrey D Peters

Anthony L Rivoli

Glenn M Friedman

Kenneth A Berry

The current gain, beta, of a vertical transistor having an emitter formed in an epitaxial base on a substrate collector is reduced by forming a high impurity region of the conductivity type of the base at the base-collector boundary to increase the base width greater than the vertical distance between the emitter and collector. A plurality of vertical transistors having identical emitters and a common collector may be simultaneously fabricated with different current gains by individually selecting the horizontal dimensions of the buried high impurity regions.

Reduced beta vertical transistors and method of fabrication

An amorphous semiconductor device on a silicon substrate having a first level contact and interconnect of aluminum and coextensive layer of molybdenum and a second level contact and interconnect of molybdenum and coextensive layer of aluminum. Contacts to the amorphous device are by the two molybdenum layers and the contact of the second level contacts to the substrate is through the first level contacts. The method of fabrication includes forming a first aluminum layer on and through contact openings in a first insulating layer and a first layer of molybdenum on the aluminum, coetching these layers to form first level contacts and interconnects forming a second layer of insulating material, forming a layer of amorphous semiconductor material through an opening in the second insulating layer; forming a second layer of molybdenum over the substrate and through contact openings in the second insulating layer and a second layer of aluminum on the second layer of molybdenum, and coetching the second layers of molybdenum and aluminum to form second level contacts and interconnects.

Amorphous devices and interconnect system and method of fabrication

A silicon substrate integrated circuit having a layer of aluminum forming Schottky contacts with lightly doped N conductivity regions and silicon doped aluminum forming ohmic contacts to heavily doped N conductivity regions and forming interconnects between contacts.

Aluminum Schottky contacts and silicon-aluminum interconnects for

A bipolar transistor process and device wherein the transistor is fabricated within a laterally isolated device region, into which is formed a lateral intradevice isolation groove prior to formation of device/active and contact regions. The lateral intradevice isolation groove with the lateral device isolation assists in self-alignment of device regions. The lateral intradevice isolation permits the simultaneous formation through a single mask of an active region and a contact region for a different active region both on the same planar surface of a semiconductor substrate and facilitates extremely close spacing of active regions at the planar surface.

Method of fabricating self-aligned bipolar transistor process and device

A metallic ground grid is fabricated by forming a conductor on the isolation barrier of an integrated circuit through openings in a first insulated layer to a depth less than the first insulated layer, forming a second insulated layer on said first conductor to the height of the first insulated layer, and interconnecting selected areas of the integrated circuit and the first conductor through openings in the insulated layers by a second conductor.

Process for forming metallic ground grid for integrated circuits

PROM wafers having fuses on raised oxide are reworked by stripping the fuses and connectors, non-selectively etching the oxide layer to form a substantially planar, oxide surface resulting from the differential etching rate of the heavily phosphorus doped raised oxide surface compared to the remainder of lightly doped oxide, increasing the oxide layer thickness and forming new fuses and connectors on the new oxide.

Method of reworking PROMS

In a complementary pair of bipolar transistors, one vertical and one lateral, the vertical transistor includes a heavily doped buried emitter, lightly doped buried graded base and a heavily doped surface collector and the lateral transistor includes a lightly doped substrate base and heavily doped emitter and collector. The lateral transistor's collector isolates the lateral transistor's base from the vertical transistor's collector. This integrated circuit approach includes the I.sup.2 L structure of the present invention and T.sup.2 L devices. The I.sup.2 L transistors are in dielectrically isolated regions with the vertical transistors emitter being connected to the polycrystalline support through a vertical opening in the dielectric isolation. The process of fabrication includes forming the vertical transistor's base by diffusion into a first surface of a substrate of opposite conductivity type, forming the vertical transistor's emitter epitaxially on the first surface and forming the vertical transistor's collector and the lateral transistor's emitter and collector by diffusion into the opposite surface of the substrate. The lateral transistor's collector diffusion is from the opposite surface down to the vertical transistor's base and separates the vertical transistor's collector from the portion of the substrate which is the lateral transistor's base. For integrated circuits, the process includes dividing the substrate into a plurality of dielectrically insulated regions after forming the epitaxial emitter and depositing a polycrystalline support.

Process of fabricating an improved I.sup.2 L integrated circuit

In a complementary pair of bipolar transistors, one vertical and one lateral, the vertical transistor includes a heavily doped buried emitter, lightly doped buried graded base and a heavily doped surface collector and the lateral transistor includes a lightly doped substrate base and heavily doped emitter and collector. The lateral transistor's collector isolates the lateral transistor's base from the vertical transistor's collector. This integrated circuit approach includes the I.sup.2 L structure of the present invention and T.sup.2 L devices. The I.sup.2 L transistors are in dielectrically isolated regions with the vertical transistors emitter being connected to the polycrystalline support through a vertical opening in the dielectric isolation. The process of fabrication includes forming the vertical transistor's base by diffusion into a first surface of a substrate of opposite conductivity type, forming the vertical transistor's emitter epitaxially on the first surface and forming the vertical transistor's collector and the lateral transistor's emitter and collector by diffusion into the opposite surface of the substrate. The lateral transistor's collector diffusion is from the opposite surface down to the vertical transistor's base and separates the vertical transistor 's collector from the portion of the substrate which is the lateral transistor's base. For integrated circuits, the process includes dividing the substrate into a plurality of dielectrically insulated regions after forming the epitaxial emitter and depositing a polycrystalline support.

I.sup.2 L Integrated circuit and process of fabrication

A method of forming fuses and two level interconnects including applying a layer of fusible material on an insulating layer and through contact apertures, cleaning said fusible layer by sputter etching, applying a layer of metallic material by sputtering, selectively patterning the metallic layer to form a top layer of contacts and interconnects and selectively patterning the fusible layer to form fusible elements and to form a bottom layer of contacts and interconnects.

Method of fabricating two level interconnects and fuse on an IC

Isolation of device locations in a monolithic semiconductor integrated circuit is provided by depositing a thin film effective as a polishing stop on a planar surface of the semiconductor body in which the devices are to be fabricated, etching isolation grooves into the body through the thin film, coating the surfaces of the grooves and the film with an insulator layer, and growing polycrystalline material over the insulator layer to fill the grooves. The polycrystalline material in excess of that required to fill the grooves, and any insulator layer covering the planar surface of the thin film, are polished away without affecting the underlying planar surface of the semiconductor body, because the thin film is adapted to withstand polishing without damage. Finally, the thin film is stripped away leaving semiconductor islands having a planar surface and isolated by insulator layer-polycrystalline material filled moats. Devices are fabricated in these islands.

Device isolation in integrated circuits

A metallic ground conductor grid applied over a planar isolation barrier in an integrated circuit provides a low resistance ground. An insulating layer, formed over the ground conductor, has apertures therein for interconnecting selected areas of the integrated circuit to the ground conductor grid.

Growing community of inventors

Melbourne Beach, FL, United States of America

William R Morcom