National Semiconductor Corporation

William Max Coppock

Charles A Dark

Terry Lee Lines

Victor Torres

Richard W Foote, Jr

Andy Strachan

Rodney L Hill

Jeffery Lee Nilles

Tom Bold

Richard Wendell Foote, Jr

Darren Lee Rust

A buried thin film resistor having end caps defined by a dielectric mask is disclosed. A thin film resistor is formed on an integrated circuit substrate. A resistor protect layer is formed over the thin film resistor. A layer of dielectric material is formed over the resistor protect layer. The dielectric material is masked and dry etched to leave a first portion of dielectric material over a first end of the thin film resistor and a second portion of dielectric material over a second end of the thin film resistor. The resistor protect layer is then wet etched using the first and second portions of the dielectric material as a hard mask. Then a second dielectric layer is deposited and vias are etched down to the underlying portions of the resistor protect layer.

System and method for providing a buried thin film resistor having end caps defined by a dielectric mask

A silicide bridged anti-fuse and a method of forming the anti-fuse are disclosed. The silicide bridged anti-fuse can be formed with a tungsten plug metalization process that does not require any additional process steps. As a result, anti-fuses can be added to an electrical circuit as trim elements for no additional cost.

Method of forming a silicide bridged anti-fuse with a tungsten plug metalization process

A method is disclosed for controlling the formation of an interfacial oxide layer in a polysilicon emitter transistor device. The interfacial oxide layer is formed between an underlying substrate of single crystal silicon and an upper layer of polysilicon. The current gain and the emitter resistance of the transistor device are related to the thickness of the interfacial oxide layer. The oxide of the interfacial oxide layer is grown in a low pressure, low temperature pure oxygen (O) environment that greatly reduces the oxidation rate. The low oxidation rate allows the thickness of the interfacial oxide layer to be precisely controlled and sources of variation to be minimized in the manufacturing process.

System and method for controlling the formation of an interfacial oxide layer in a polysilicon emitter transistor

A system and method is disclosed for selectively increasing a wet etch rate of a large raised area portion of a semiconductor wafer with respect to a wet etch rate of a small raised area portion of the semiconductor wafer. A resist mask on the semiconductor wafer is etched to create a large via over the large raised area portion and a small via over the small raised area portion. An ion implantation beam is applied with an impact direction that enables ions to pass through the large via but does not enable ions to pass through the small via. The ions that pass through the large via increase the wet etch rate of the underlying portion of the semiconductor wafer. In one embodiment the impact direction has a tilt angle of forty five degrees and a rotation angle of forty five degrees.

System and method for selectively modifying a wet etch rate in a large area

A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming a plurality of trenches between the first and second regions, implanting a dopant into the bottom surfaces of the trenches, and then annealing the wafer to cause the dopant at the bottom surfaces to diffuse and form a continuous conductive path.

Method of forming a conductive structure

A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming one or more trenches between the first and second regions, and implanting a dopant into the bottom surfaces of the trenches to form a continuous conductive path.

Method of forming a conductive structure in a semiconductor material

Conductive structure in a semiconductor material

Silicide bridged anti-fuse

Conductive structure and method of forming the structure

The present invention provides a two-terminal Zener zap diode device structure that relies upon the formation of an anti-fuse through a silicon substrate with the melting and flow of an aluminum alloy to create the current path. The use of oversized contacts in the diode structure permits the Tungsten plug to be eliminated from the diode structure and, thus, permits an aluminum alloy melt and flow mechanism to be used with a Tungsten plug process.

Method of adding Zener zap aluminum bridged anti-fuses to a tungsten plug process

A three-terminal integrated circuit device structure is provided that relies upon the formation of an anti-fuse through a silicon substrate with the melting and flowing of an aluminum/aluminum alloy to create the current path. The use of an oversized contact permits the Tungsten plug to be eliminated from the anti-fuse structure, but allows the aluminum melt and flow mechanism to be used with a Tungsten plug process.

Growing community of inventors

Arlington, TX, United States of America

William Max Coppock