Hrl Laboratories, LLC

Hughes Aircraft Company

Hughes Electronics Corporation

Raytheon Company

Promtek

The United States of America as Represented by the United States

Oregon Graduate Center

Raytheon Corporation

William M Clark, Jr

Lap-Wai Chow

James Peter Baukus

Gavin J Harbison

Lap Wai Chow

Paul Yang

Mark W Utlaut

David B Shu

Charles M McKenna

Allan R Kramer

Lynwood W Swanson

Paul Ouyang

Edmund K Storms

Robert G Behrens

Eugene G Szklarz

William L Johnson

Robert L Seliger

Joseph A Wysocki

Gary M Atkinson

Robert H Walden

Anthony E Bell

Wing Y Lum

James R Herring

Peter B Back

Irwin R Sharapata

Robert P Santandrea

A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable.

Use of silicide block process to camouflage a false transistor

A technique for and structures for camouflaging an integrated circuit structure and strengthen its resistance to reverse engineering. A plurality of transistors are formed in a semiconductor substrate, at least some of the transistors being of the type having sidewall spacers with LDD regions formed under the sidewall spacers. Transistors are programmably interconnected with ambiguous interconnection features, the ambiguous interconnection features each comprising a channel formed in the semiconductor substrate with preferably the same dopant density as the LDD regions, with selected ones of the channels being formed of a conductivity type supporting electrical communication between interconnected active regions and with other selected ones of the channels being formed of a conductivity type inhibiting electrical communication but ambiguously appearing to a reverse engineer as supporting electrical communication.

Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer

A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions regardless of any reasonable voltage applied to the integrated circuit structure.

Integrated circuit modification using well implants

An apparatus and method for preventing information leakage attacks through a polarized cryptographic bus architecture. The polarized cryptographic bus architecture randomly changes the polarity of the target bit such that the leaked information cannot be consistently averaged to yield statistical key material. Further, to increase the prevention of information leakage attacks, a set of dual rails is used to write data to a given register bit.

Cryptographic bus architecture for the prevention of differential power analysis

A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among said plurality of layers to provide artifact edges of the conductive material that resemble one type of transistor (operable vs. non-operable), when in fact another type of transistor was used.

Conductive channel pseudo block process and circuit to inhibit reverse engineering

An apparatus and method for preventing information leakage attacks that utilize timeline alignment. The apparatus and method inserts a random number of instructions into an encryption algorithm such that the leaked information can not be aligned in time to allow an attacker to break the encryption.

Cryptographic architecture with random instruction masking to thwart differential power analysis

A technique for and structures for camouflaging an integrated circuit structure. The technique including forming active areas of a first conductivity type and LDD regions of a second conductivity type resulting in a transistor that is always non-operational when standard voltages are applied to the device.

Symmetric non-intrusive and covert technique to render a transistor permanently non-operable

Cryptographic CPU architecture with random instruction masking to thwart differential power analysis

A technique for and structures for camouflaging an integrated circuit structure. The technique includes the use of a light density dopant (LDD) region of opposite type from the active regions resulting in a transistor that is always off when standard voltages are applied to the device.

Covert transformation of transistor properties as a circuit protection method

Use of silicon block process step to camouflage a false transistor

Semiconducting devices, including integrated circuits, protected from reverse engineering comprising metal traces leading to field oxide. Metallization usually leads to the gate, source or drain areas of the circuit, but not to the insulating field oxide, thus misleading a reverse engineer. A method for fabricating such devices.

Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide

Growing community of inventors

Camarillo, CA, United States of America

William M Clark, Jr